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| author | Jett Rink <jettrink@chromium.org> | 2018-03-22 10:18:49 -0600 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-26 17:03:27 -0700 |
| commit | 6a7fb0d39bf84d7199f0a3f1f9a32cd85dc1113e (patch) | |
| tree | 66ed0813f563bb89527da05dbb1fa884b0e86df7 /include/lpc.h | |
| parent | b57ad0e1b82f87e7882e3bd7d05b8e994ad5a414 (diff) | |
| download | chrome-ec-6a7fb0d39bf84d7199f0a3f1f9a32cd85dc1113e.tar.gz | |
lpc: remove lpc_host_reset
No one is using this method and it implies that all chipset should
support the RCIN# Virtual Wire if using eSPI. Only large core chips
use RCIN#; small core chips don't.
This method was introduced for skylake and has since been replaced
since CL:575947 was merged.
BRANCH=none
BUG=none
TEST=build all
Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/975904
Diffstat (limited to 'include/lpc.h')
| -rw-r--r-- | include/lpc.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/include/lpc.h b/include/lpc.h index c95999a98e..4f00d2cc3a 100644 --- a/include/lpc.h +++ b/include/lpc.h @@ -125,11 +125,6 @@ void lpc_clear_acpi_status_mask(uint8_t mask); */ int lpc_get_pltrst_asserted(void); -/** - * Reset the host with KBRST# or RCIN# - */ -void lpc_host_reset(void); - /* Disable LPC ACPI interrupts */ void lpc_disable_acpi_interrupts(void); |