diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2019-06-10 16:26:36 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-06-11 17:26:38 +0000 |
| commit | 59d060ebfe68082f4ea87214ffcda976c55176af (patch) | |
| tree | e237e25e9979220a716b72b65d43fb559504bc60 /include/panic.h | |
| parent | 3a668749460466ff002b5dd2cbf00529f97e5974 (diff) | |
| download | chrome-ec-59d060ebfe68082f4ea87214ffcda976c55176af.tar.gz | |
core:RISC-V / chip:IT83202
The IT83202 is an embedded controller with RISC-V core.
It supports maximum ram size to 256KB and internal flash to 1MB.
BUG=none
BRANCH=none
TEST=EC boots and test console commands (eg: taskinfo, version, sysjump...)
on it83202 EVB.
Change-Id: I424c0d2878beb941c816363b5c7a3f57fda9fd13
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1588300
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'include/panic.h')
| -rw-r--r-- | include/panic.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/panic.h b/include/panic.h index f3bccd18a0..afbe4b9357 100644 --- a/include/panic.h +++ b/include/panic.h @@ -41,6 +41,13 @@ struct nds32_n8_panic_data { uint32_t ipsw; }; +/* RISC-V RV32I registers saved on panic */ +struct rv32i_panic_data { + uint32_t regs[31]; /* sp, ra, gp, tp, a0-a7, t0-t6 s0-s11 */ + uint32_t mepc; /* mepc */ + uint32_t mcause; /* mcause */ +}; + /* x86 registers saved on panic */ struct x86_panic_data { uint32_t vector; /* Exception vector number */ @@ -72,6 +79,7 @@ struct panic_data { struct cortex_panic_data cm; /* Cortex-Mx registers */ struct nds32_n8_panic_data nds_n8; /* NDS32 N8 registers */ struct x86_panic_data x86; /* Intel x86 */ + struct rv32i_panic_data riscv; /* RISC-V RV32I */ }; /* @@ -87,6 +95,7 @@ enum panic_arch { PANIC_ARCH_CORTEX_M = 1, /* Cortex-M architecture */ PANIC_ARCH_NDS32_N8 = 2, /* NDS32 N8 architecture */ PANIC_ARCH_X86 = 3, /* Intel x86 */ + PANIC_ARCH_RISCV_RV32I = 4, /* RISC-V RV32I */ }; /* Use PANIC_DATA_PTR to refer to the persistent storage location */ |