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| author | Caveh Jalali <caveh@chromium.org> | 2021-02-04 02:08:08 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-02-07 08:00:38 +0000 |
| commit | beaa1254449978a3d83ec49df10da2ffa6ad22c8 (patch) | |
| tree | 1a90c4dfb6dd232b0c713728a39d176f61a46117 /include/power/intel_x86.h | |
| parent | 66b9dd413a5e2319456271f8594a6a879e6f3941 (diff) | |
| download | chrome-ec-beaa1254449978a3d83ec49df10da2ffa6ad22c8.tar.gz | |
alderlake: Implement chipset support
This provides support for the Intel Alder Lake SoC in conjunction with
the Silergy SLG4BD44540 power sequencer.
A new config option (CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) is provided
to enable this setup.
This is intended to be used by brya and its variants. Other Alder Lake
boards that use the Ice Lake style power sequencing are not affected by
this new config option.
BRANCH=none
BUG=b:173575131,b:177275055,b:177277633
TEST=buildall passes
Change-Id: I74c36f06fc8ad26c163093753140a5ca242d75c7
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2675309
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'include/power/intel_x86.h')
| -rw-r--r-- | include/power/intel_x86.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/power/intel_x86.h b/include/power/intel_x86.h index d50d6a75da..303db20de7 100644 --- a/include/power/intel_x86.h +++ b/include/power/intel_x86.h @@ -13,8 +13,10 @@ #include "power.h" /* Chipset specific header files */ +#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) +#include "alderlake_slg4bd44540.h" /* Geminilake and apollolake use same power sequencing. */ -#ifdef CONFIG_CHIPSET_APL_GLK +#elif defined(CONFIG_CHIPSET_APL_GLK) #include "apollolake.h" #elif defined(CONFIG_CHIPSET_CANNONLAKE) #include "cannonlake.h" |