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authorGwendal Grignou <gwendal@chromium.org>2015-07-25 02:14:13 -0700
committerChromeOS Commit Bot <chromeos-commit-bot@chromium.org>2015-07-30 19:57:55 +0000
commit5b71b33aba6cb0108a864cc7000918b8f06b139a (patch)
treeaa49a59a306d91b189e9fcdddc3bbb0e2deba628 /include/spi.h
parent9008c7a4fd131a96ccb0078a46ec545cff2f43b1 (diff)
downloadchrome-ec-5b71b33aba6cb0108a864cc7000918b8f06b139a.tar.gz
common: change interface to SPI flash
Allow more than one SPI master. Add CONFIG variables to address the system SPI flash. To have SPI master ports, spi_ports array must be defined. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288512 Commit-Queue: David James <davidjames@chromium.org>
Diffstat (limited to 'include/spi.h')
-rw-r--r--include/spi.h57
1 files changed, 50 insertions, 7 deletions
diff --git a/include/spi.h b/include/spi.h
index d62c1420ca..21629ddd4d 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -27,26 +27,69 @@ enum spi_clock_mode {
SPI_CLOCK_MODE3 = 3
};
-/* Enable / disable the SPI port. When the port is disabled, all its I/O lines
- * are high-Z so the EC won't interfere with other devices on the SPI bus. */
-int spi_enable(int enable);
+struct spi_device_t {
+ /*
+ * SPI port the device is connected to.
+ * On some architecture, this is SPI master port index,
+ * on other the SPI port index directly.
+ */
+ uint8_t port;
+
+ /*
+ * Clock divisor to talk to SPI device.
+ * If several devices share the same port, we select the lowest speed.
+ */
+ uint8_t div;
+
+ /* gpio used for chip selection. */
+ enum gpio_signal gpio_cs;
+};
+
+extern const struct spi_device_t spi_devices[];
+extern const unsigned int spi_devices_used;
+
+/*
+ * The first port in spi_ports define the port to access the SPI flash.
+ * The first gpio defines the CS GPIO to access the flash,
+ * if used.
+ */
+#define SPI_FLASH_DEVICE (&spi_devices[0])
+
+/*
+ * Enable / disable the SPI port. When the port is disabled, all its I/O lines
+ * are high-Z so the EC won't interfere with other devices on the SPI bus.
+ *
+ * @param port port id to work on.
+ * @param enable 1 to enable the port, 0 to disable it.
+ */
+int spi_enable(int port, int enable);
/* Issue a SPI transaction. Assumes SPI port has already been enabled.
+ *
* Transmits <txlen> bytes from <txdata>, throwing away the corresponding
* received data, then transmits <rxlen> dummy bytes, saving the received data
- * in <rxdata>. */
-int spi_transaction(const uint8_t *txdata, int txlen,
+ * in <rxdata>.
+ *
+ * @param spi_device the SPI device to use
+ * @param txdata buffer to transmit
+ * @param txlen number of bytes in txdata.
+ * @param rxdata receive buffer.
+ * @param rxlen number of bytes in rxdata.
+ */
+int spi_transaction(const struct spi_device_t *spi_device,
+ const uint8_t *txdata, int txlen,
uint8_t *rxdata, int rxlen);
/* Similar to spi_transaction(), but hands over to DMA for reading response.
* Must call spi_transaction_flush() after this to make sure the response is
* received.
*/
-int spi_transaction_async(const uint8_t *txdata, int txlen,
+int spi_transaction_async(const struct spi_device_t *spi_device,
+ const uint8_t *txdata, int txlen,
uint8_t *rxdata, int rxlen);
/* Wait for async response received */
-int spi_transaction_flush(void);
+int spi_transaction_flush(const struct spi_device_t *spi_device);
#ifdef CONFIG_SPI
/**