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| author | Scott Worley <scott.worley@microchip.corp-partner.google.com> | 2017-12-20 14:37:31 -0500 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-12-28 14:50:32 -0800 |
| commit | f8dc4617128f72cdcef4aae33afd665d3fbc5a2f (patch) | |
| tree | 7c444f354569f5308a60d85cada7d5fcb0547620 /include/spi_flash_reg.h | |
| parent | 940dd625b9edaf1827c9c3a2349a66ec21cd59c8 (diff) | |
| download | chrome-ec-f8dc4617128f72cdcef4aae33afd665d3fbc5a2f.tar.gz | |
ec_flash: Add W25Q128 SPI flash
Add W25Q128 flash device support.
BRANCH=none
BUG=
TEST=Modify a board build for W25Q128 and check
SPI code sets flash security bits correctly.
Change-Id: I6173f4cf751f3fbf68af75983f44d357a0b954f6
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Diffstat (limited to 'include/spi_flash_reg.h')
| -rw-r--r-- | include/spi_flash_reg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/spi_flash_reg.h b/include/spi_flash_reg.h index e42d9baa99..2d564e6b50 100644 --- a/include/spi_flash_reg.h +++ b/include/spi_flash_reg.h @@ -38,6 +38,11 @@ #define CONFIG_SPI_FLASH_HAS_SR2 #endif +/* W25Q128 16 Mbyte SPI flash for testing */ +#ifdef CONFIG_SPI_FLASH_W25Q128 +#define CONFIG_SPI_FLASH_HAS_SR2 +#endif + /** * Computes block write protection range from registers * Returns start == len == 0 for no protection |