diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2020-09-21 11:13:33 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-24 09:16:58 +0000 |
| commit | 0542741e0e8727ae53bce47a1fd4459735056b53 (patch) | |
| tree | 9763cda3eda742134912a49105aaf492622c24ee /include/task.h | |
| parent | 1c3c2140f333f4a169f047fad8a780d0b71c2e5d (diff) | |
| download | chrome-ec-0542741e0e8727ae53bce47a1fd4459735056b53.tar.gz | |
it83xx: read_clear_int_mask() read and clear interrupt bit.
This change pulled the operation of interrupt disable into
read_clear_int_mask().
Because riscv core supports instruction csrrc to atomic read and
clear bit in CSR register. With this change, we won't need to separate
operations of reading and clearing interrupt bit on riscv core.
BUG=none
BRANCH=none
TEST=read_clear_int_mask() is able to disable interrupt and return
saved interrupt bit on both nds32 and riscv cores.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I871aab747b950b7948cdeb7911fcf8c09d55df5d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2419739
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'include/task.h')
| -rw-r--r-- | include/task.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/include/task.h b/include/task.h index a0db186eb4..0b244a2a18 100644 --- a/include/task.h +++ b/include/task.h @@ -90,11 +90,11 @@ int in_interrupt_context(void); int in_soft_interrupt_context(void); /** - * Return current interrupt mask. Meaning is chip-specific and - * should not be examined; just pass it to set_int_mask() to - * restore a previous interrupt state after interrupt_disable(). + * Return current interrupt mask with disabling interrupt. Meaning is + * chip-specific and should not be examined; just pass it to set_int_mask() to + * restore a previous interrupt state after interrupt disable. */ -uint32_t get_int_mask(void); +uint32_t read_clear_int_mask(void); /** * Set interrupt mask. As with interrupt_disable(), use with care. |