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| author | Scott Collyer <scollyer@google.com> | 2021-03-10 21:43:46 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-12 17:55:59 +0000 |
| commit | 42051e03688e24b0a3550306f15c66edc2313f32 (patch) | |
| tree | 30588d66a548c064afd8cd26acb44641aee8bbec /include/usb_pd.h | |
| parent | 3eeaf9c10014218f84bf5f797eb6f5d78a419f3e (diff) | |
| download | chrome-ec-42051e03688e24b0a3550306f15c66edc2313f32.tar.gz | |
TCPMv2: Add support for disabling type-2 BIST mode
This CL adds a TCPCI method to disable BIST mode for the case where
the TCPC does not handle the duration automatically. This is required
for the ucpd driver as once type-2 BIST mode is started, the ucpd
peripheral needs to be reset to stop.
This CL also reduces the timer value from 60 msec to 55 msec to ensure
that there is enough time for BIST to be stopped and still be in spec.
BUG=b:182436876
BRANCH=None
TEST=verifed on Quiche that when type-2 BIST is started then it stops
when the timer in PE expires. This fixes TDA.2.1.1.1: BMC-PHY-TX-EYE
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I59ee7ac0dead09ac3a1b5783cfa3fe9db238eb7e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2660803
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'include/usb_pd.h')
| -rw-r--r-- | include/usb_pd.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/usb_pd.h b/include/usb_pd.h index 8c5da1c865..81dbc3220a 100644 --- a/include/usb_pd.h +++ b/include/usb_pd.h @@ -228,7 +228,7 @@ enum pd_rx_errors { #define PD_T_NO_RESPONSE (5500*MSEC) /* between 4.5s and 5.5s */ #define PD_T_BIST_TRANSMIT (50*MSEC) /* 50ms (for task_wait arg) */ #define PD_T_BIST_RECEIVE (60*MSEC) /* 60ms (time to process bist) */ -#define PD_T_BIST_CONT_MODE (60*MSEC) /* 30ms to 60ms */ +#define PD_T_BIST_CONT_MODE (55*MSEC) /* 30ms to 60ms */ #define PD_T_VCONN_SOURCE_ON (100*MSEC) /* 100ms */ #define PD_T_DRP_TRY (125*MSEC) /* between 75ms and 150ms */ #define PD_T_TRY_TIMEOUT (550*MSEC) /* between 550ms and 1100ms */ |