diff options
author | Mary Ruthven <mruthven@chromium.org> | 2022-04-25 13:43:36 -0500 |
---|---|---|
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-04-27 14:11:48 +0000 |
commit | 76d059d1441f3d87b38b100a2a477ac0d73b1cc7 (patch) | |
tree | 7a4201d82e76cd23699019ef08ee0a40d08bc5b2 /include | |
parent | 0ab123eac0939364c96c07ed279148864c3e41fd (diff) | |
download | chrome-ec-76d059d1441f3d87b38b100a2a477ac0d73b1cc7.tar.gz |
gpio: add gpio flags to disable sleep
Add GPIO_SLEEP_DIS_LOW and GPIO_SLEEP_DIS_HIGH to disable sleep when a
gpio with one of those flags is asserted.
GPIO_SLEEP_DIS_LOW disables sleep when the signal is set to 0.
GPIO_SLEEP_DIS_HIGH disables sleep when the signal is set to 1.
This will disable all forms of sleep. The flags can be used for ccd
signals to ensure cr50 doesn't enter sleep while c2d2 or servo micro are
relying on a ccd signal to flash the device.
These flags should not be add to signals used during normal cr50
operation. They disable regular sleep regular sleep so using them will
significantly increase cr50 power consumption.
This change adds GPIO_SLEEP_DIS_HIGH to AP_FLASH_SELECT. I'll add more
signals in followup CLs.
This change also replaces SLEEP_MASK_CHARGING with SLEEP_MASK_GPIO.
Nothing was using SLEEP_MASK_CHARGING.
BUG=b:229974371
TEST=Toggle AP_FLASH_SELECT while the AP is off. Verify cr50 doesn't
enter deep sleep and the gpiocfg and sleepmask output looks ok.
> gpioset AP_FLASH_SELECT 1
> gpiocfg
GPIO0_GPIO1: read 0 drive 0
GPIO0_GPIO2: read 1 drive 1
GPIO1_GPIO0: read 0 INT_RISING
GPIO1_GPIO1: read 0 INT_HIGH
GPIO1_GPIO4: read 0 INT_FALLING
GPIO1_GPIO5: read 0 drive 1
GPIO1_GPIO7: read 0 INT_RISING
GPIO1_GPIO8: read 0 INT_FALLING
gpio sleepmask: 00001000
> sleepmask
sleep mask: 00000008
> gpioset AP_FLASH_SELECT 0
> gpiocfg
GPIO0_GPIO1: read 0 drive 0
GPIO0_GPIO2: read 0 drive 0
GPIO1_GPIO0: read 0 INT_RISING
GPIO1_GPIO1: read 0 INT_HIGH
GPIO1_GPIO4: read 0 INT_FALLING
GPIO1_GPIO5: read 0 drive 1
GPIO1_GPIO7: read 0 INT_RISING
GPIO1_GPIO8: read 0 INT_FALLING
gpio sleepmask: 00000000
> sleepmask
sleep mask: 00000000
>
Change-Id: I1de35455c5a6702635fb714b14d6791f8e5eb2ed
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3605881
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/config.h | 3 | ||||
-rw-r--r-- | include/gpio.h | 7 | ||||
-rw-r--r-- | include/system.h | 2 |
3 files changed, 11 insertions, 1 deletions
diff --git a/include/config.h b/include/config.h index b37144331f..f48a640d68 100644 --- a/include/config.h +++ b/include/config.h @@ -1807,6 +1807,9 @@ /* Support getting gpio flags. */ #undef CONFIG_GPIO_GET_EXTENDED +/* Support disabling sleep with GPIO flags. */ +#undef CONFIG_GPIO_DISABLE_SLEEP + /* Do we want to detect the lid angle? */ #undef CONFIG_LID_ANGLE diff --git a/include/gpio.h b/include/gpio.h index b0291b40f1..07d46dd055 100644 --- a/include/gpio.h +++ b/include/gpio.h @@ -37,6 +37,13 @@ #define GPIO_HIB_WAKE_LOW BIT(20) /* Hibernate wake on low level */ #define GPIO_HIB_WAKE_RISING BIT(21) /* Hibernate wake on rising edge */ #define GPIO_HIB_WAKE_FALLING BIT(22) /* Hibernate wake on falling edge */ +/* + * The SLEEP_DIS flags disable sleep when they're asserted. They disable regular + * and deep sleep, so they shouldn't be asserted as a part of normal operation. + * These flags should ONLY be used on debug signals. + */ +#define GPIO_SLEEP_DIS_LOW BIT(23) /* Disable sleep when set to 0. */ +#define GPIO_SLEEP_DIS_HIGH BIT(24) /* Disable sleep when set to 1. */ /* Common flag combinations */ #define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW) diff --git a/include/system.h b/include/system.h index 9826dfa17f..49a85e6eb9 100644 --- a/include/system.h +++ b/include/system.h @@ -359,7 +359,7 @@ enum { SLEEP_MASK_UART = BIT(1), /* UART communication ongoing */ SLEEP_MASK_I2C_CONTROLLER = BIT(2), /* I2C communication ongoing */ - SLEEP_MASK_CHARGING = BIT(3), /* Charging loop ongoing */ + SLEEP_MASK_GPIO = BIT(3), /* GPIO activity ongoing */ SLEEP_MASK_USB_PWR = BIT(4), /* USB power loop ongoing */ SLEEP_MASK_USB_PD = BIT(5), /* USB PD device connected */ SLEEP_MASK_SPI = BIT(6), /* SPI communications ongoing */ |