diff options
| author | CHLin <CHLin56@nuvoton.com> | 2020-09-28 10:19:43 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-10-05 10:07:41 +0000 |
| commit | e6ca724f8b5e15a18bccf14c5905b3f1d8baf7c2 (patch) | |
| tree | b69ce7c30a19297c151202a977ff317f8a5c8666 /include | |
| parent | fe6577ffb515ef35af32a109e2b0832ea6a24018 (diff) | |
| download | chrome-ec-e6ca724f8b5e15a18bccf14c5905b3f1d8baf7c2.tar.gz | |
npcx: support enhanced PSL functions in npcx9
1. In npcx7, the PSL (hibernation) wakeup source only can come from
physical PSL_IN pins. In npcx9, the LCT (Long Countdown Timer)
module is introduced to support wakeup from a configurable timeout.
2. support PSL wakeup from the VCC1_RST pin. This function is disabled
by default and enabled (and locked) in the firmware in the npcx9 A1
chip. In the npcx9 A2 chip, this function is enabled (and locked)
by booter.
3. Support pulse mode and open drain (if pulse mode is enabled) for
PSL_OUT pin.
4. support one PSL general-purpose output pin which is powered by VSBY.
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST="hibernate 10", check EC wakes up from hibernate after 10 seconds.
make sure the reset cause in the console is "power-on hibernate
rtc-alarm"
TEST="hibernate"; check EC wakes up from hibernate after pressing
VCC1_RST button on the internal test board.
Test=configure the PSL_OUT to pulse mode and "hibernate"; cut off VCC1
power; check EC can wake up from hibernate with any input event.
Test=configure the level of PSL_GPO before hibernation; check the level
is kept after entering hibernation.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I98ad41da8557222cf3d09fef9524880731cecde1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435164
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/config.h | 22 | ||||
| -rw-r--r-- | include/rtc.h | 5 |
2 files changed, 26 insertions, 1 deletions
diff --git a/include/config.h b/include/config.h index 057046517d..2a5f86377d 100644 --- a/include/config.h +++ b/include/config.h @@ -2241,6 +2241,28 @@ /* Wake up pins have non-const configuration. */ #undef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC +/* In npcx9 and later chips, enhanced PSL features are supported including: + * (1) Pulse mode for PSL_OUT signal. + * (2) Open-drain for PSL_OUT signal (when Pulse mode is enabled.) + * These features can be enabled in board configuration file by adding + * the following bit masks to this flag: + * (1) NPCX_PSL_CFG_PSL_OUT_PULSE. + * (2) NPCX_PSL_CFG_PSL_OUT_OD. + * Ex: #define CONFIG_HIBERNATE_PSL_OUT_FLAGS \ + (NPCX_PSL_CFG_PSL_OUT_PULSE | NPCX_PSL_CFG_PSL_OUT_OD) + */ +#undef CONFIG_HIBERNATE_PSL_OUT_FLAGS + +/* + * Enable VCC1_RST pin as the input of PSL wakeup source. When Enabling this, + * the VCC1_RST pin must be connected to the VSBY supply via an external pull-up + * resistor of maximum 100K ohm . + * TODO: Remove this when NPCX9 A2 chip is available because A2 + * chip will enable VCC1_RST to PSL wakeup source and lock it in + * the booter. + */ +#undef CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP + /* * Chip supports a 64-bit hardware timer and implements * __hw_clock_source_read64 and __hw_clock_source_set64. diff --git a/include/rtc.h b/include/rtc.h index c9909bbc48..cff1ee0f64 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -10,7 +10,10 @@ #include "common.h" -#define SECS_PER_DAY (60 * 60 * 24) +#define SECS_PER_MINUTE 60 +#define SECS_PER_HOUR (60 * SECS_PER_MINUTE) +#define SECS_PER_DAY (24 * SECS_PER_HOUR) +#define SECS_PER_WEEK (7 * SECS_PER_DAY) #define SECS_PER_YEAR (365 * SECS_PER_DAY) /* The seconds elapsed from 01-01-1970 to 01-01-2000 */ #define SECS_TILL_YEAR_2K (946684800) |