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author | CHLin <CHLIN56@nuvoton.com> | 2017-04-21 15:32:45 +0800 |
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committer | chrome-bot <chrome-bot@chromium.org> | 2017-04-25 01:45:44 -0700 |
commit | 579a6b00e5b4f31bf3dbefd82aa19fb52b6905bb (patch) | |
tree | 72da72618cab8f12b2a15cbb9370620b82b5a7a1 /include | |
parent | b95463cf3c6ef6c59e0d431fcbd8e71ae8ec86a4 (diff) | |
download | chrome-ec-579a6b00e5b4f31bf3dbefd82aa19fb52b6905bb.tar.gz |
npcx: i2c: Fix i2c freq setting when APB clock is 15 MHz
To configure 1 MHz speed when the APB clock is 15 MHz, the firmware
currently sets the SCLHT register to 4. However, we found out that
writing 4 to this register (and to SCLLT register) is illegal and
results in unexpected results. So there is a need to write 5 in that
case. However, this means that the actual i2c frequency will be 750 KHz.
To get a higher i2c clock frequency, there is a need to run with a
higher APB clock (and a higher core clock). For example, with APB set to
20 MHz, the i2c clock frequency is 833 KHz.
In this CL, the i2c freq setting for APB clock=20 MHz is also added which
may be used for NPCX7 in the future.
BRANCH=none
BUG=chromium:714314
TEST=No build error for make buildall(except gru). Use scope to capture
SCL signal on npcx5 EVB and make sure its freqency is about 750 KHz.
Change-Id: I9025344e6df4b584b203c8c59bb9875250d9fe4f
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/484202
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions