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| author | Scott Collyer <scollyer@google.com> | 2019-01-31 17:00:44 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-02-04 22:49:20 -0800 |
| commit | 03c345ddb00961f3f2adc8926c7a0d72167b849a (patch) | |
| tree | b36331fb18b03b6ea252a7780b0cea5c1de593b1 /include | |
| parent | ce8939ec86a348c25af32a0e07aadd6054f510a8 (diff) | |
| download | chrome-ec-03c345ddb00961f3f2adc8926c7a0d72167b849a.tar.gz | |
cometlake: EC should not delay RSMRST_L by 10 msec
The PCH wants 10 msec delay between PP1050_A being valid prior to
RSMRST_L transitioning from low to high. In other big core chips this
has been enforced by the EC adding a 10 msec sleep before passing
RSMRST_L to the AP. However on Cometlake this delay is handled by the
Silego part, so the EC does not need to add any additional delay.
BRANCH=none
BUG=b:123751590
TEST=Verified that the delay from PP1050 rising to RSMRST_L rising is
now 10 msec and not 20 msec as it was prior to this change.
Change-Id: Iab463169a81579f64aa5957662d268adbde6a57c
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1448817
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/config.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/config.h b/include/config.h index 5d214c0ddc..8e54df3253 100644 --- a/include/config.h +++ b/include/config.h @@ -4167,7 +4167,7 @@ #endif #if defined(CONFIG_CHIPSET_SKYLAKE) || defined(CONFIG_CHIPSET_CANNONLAKE) \ - || defined(CONFIG_CHIPSET_ICELAKE) || defined(CONFIG_CHIPSET_COMETLAKE) + || defined(CONFIG_CHIPSET_ICELAKE) #define CONFIG_CHIPSET_X86_RSMRST_DELAY #endif |