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| author | Yilun Lin <yllin@google.com> | 2019-03-20 17:26:49 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-05-02 05:38:25 -0700 |
| commit | 4ffa4bb861612f9debffc9088bac72a1ac611ff5 (patch) | |
| tree | 6b381e78bdec26297d8d04d9f3767f07cd322e3e /include | |
| parent | 19915c08ec2828235d5db7b0d3a990ab165649cd (diff) | |
| download | chrome-ec-4ffa4bb861612f9debffc9088bac72a1ac611ff5.tar.gz | |
kukui_scp: Enable MPU to protect code RAM and data RAM in RW image.
kukui_scp is loaded into SRAM. We would like to protect
the memory from a modified code RAM content and executing injected
code in data RAM.
BRANCH=None
BUG=b:123269246
TEST=Apply MPU test patch https://crrev.com/c/1530265.
Test data ram XN:
1. mpu 0 # disable MPU
2. mpu_test # see it prints
3. mpu 1 # enable MPU
4. mpu_test # memory access violation, and reset.
5. mpu_test # memory access violation, and reset
# again. (MPU enabled by default)
Test code ram RO:
1. rw 0x8 0x5566 # Write to code RAM and see memory
# access violation and reset.
2. mpu 0 # disable MPU
3. rw 0x8 0x5566 # Nothing happended
4. rw 0x8 # Read 0x5566
5. mpu 1 # enable MPU
6. rw 0x8 0x5566 # memory access violation.
Change-Id: I6af5029d8c55d795543d4759b2c9168a06eb9ff1
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1530264
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/config.h | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/include/config.h b/include/config.h index 22fbe4c6f7..171938d9cc 100644 --- a/include/config.h +++ b/include/config.h @@ -2773,10 +2773,19 @@ * Usually, CONFIG_DATA_RAM_SIZE = CONFIG_RAM_SIZE but some chips need to * allocate RAM for the mask ROM. Then CONFIG_DATA_RAM_SIZE > CONFIG_RAM_SIZE. * + * CONFIG_CODE_RAM_SIZE indicates the size of all code RAM available on the chip + * in bytes. This is needed when a chip with external storage where stored with + * code section, or a chip without an internal flash but need to protect its + * code section by MPU. + * Usually, CONFIG_CODE_RAM_SIZE = CONFIG_RO_SIZE. However, some chips may + * have other value, e.g. mt_scp which doesn't have RO image, and the code RAM + * size is actually its CONFIG_ROM_SIZE plus a reserved memory space. + * * CONFIG_ROM_SIZE indicates the size of ROM allocated by a linker script. This * is only needed when no physical flash present (!CONFIG_FLASH_PHYSICAL). The * ROM region will place common RO setions, e.g. .text, .rodata, .data LMA etc. */ +#undef CONFIG_CODE_RAM_SIZE #undef CONFIG_DATA_RAM_SIZE #undef CONFIG_RAM_SIZE #undef CONFIG_ROM_SIZE @@ -4009,10 +4018,18 @@ /******************************************************************************/ /* + * Set default code ram size unless it's customized by the chip. + */ +#ifndef CONFIG_CODE_RAM_SIZE +#define CONFIG_CODE_RAM_SIZE CONFIG_RO_SIZE +#endif + +/******************************************************************************/ +/* * Set default data ram size unless it's customized by the chip. */ #ifndef CONFIG_DATA_RAM_SIZE -#define CONFIG_DATA_RAM_SIZE CONFIG_RAM_SIZE +#define CONFIG_DATA_RAM_SIZE CONFIG_RAM_SIZE #endif /******************************************************************************/ |