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| author | Evan Green <evgreen@chromium.org> | 2019-05-01 16:46:36 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-05-08 19:35:34 -0700 |
| commit | fb2a7efc26a598fa2697300d72827a285261b913 (patch) | |
| tree | a9bb9d4dd9ae6b25e091554ecc9cfa29423c5595 /include | |
| parent | 65fde9d10e35890766e279183ae061b72170299d (diff) | |
| download | chrome-ec-fb2a7efc26a598fa2697300d72827a285261b913.tar.gz | |
power: Manipulate wake mask during s0ix timeouts
When S0ix failure detection is enabled and a timeout occurs such that
the SLP_S0 line never actually toggles, then s0ix_transition_timeout()
sets the HANG_DETECT event bit. This doesn't quite work in this scenario,
since the wake mask is only enabled when the power state transitions to
S0ix, which happens when the SLP_S0 line toggles. So the AP never sees the
event, since it's not in the wake mask and so never causes the EC->AP
interrupt line to change.
Detect this situation in the timeout function, and explicitly move the
wake mask to its S0ix value so that when the event bit is set, (if it
is in the wake mask), the system will wake up.
Doing this forcefully gets the wake mask out of sync with the power state.
So upon resume, explicitly restore the wake mask to its S0 state.
BUG=b:131434497
BRANCH=none
TEST=suspend_stress_test -c1 --suspend_min=60 with a firmware where
S0ix fails.
Change-Id: Id2e67c6933a7895fba85ccfdff9b336629eabf24
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1592469
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/power.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/power.h b/include/power.h index 2c57209e84..2688852e44 100644 --- a/include/power.h +++ b/include/power.h @@ -145,6 +145,11 @@ void power_set_state(enum power_state new_state); */ enum power_state power_get_state(void); +/* + * Set the wake mask according to the current power state. + */ +void power_update_wake_mask(void); + /** * Chipset-specific initialization * |