diff options
| author | Archana Patni <archana.patni@intel.com> | 2016-02-02 19:29:05 +0530 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-02-10 12:44:15 -0800 |
| commit | 192806b8da1b8714f6bfcdc548a7e8e7866b8384 (patch) | |
| tree | 7f9cce47f9eb35a2cd25af316dc63d945a75c53f /include | |
| parent | 40018bb45ba8ab918f1c7c20f400046f8fad0be2 (diff) | |
| download | chrome-ec-192806b8da1b8714f6bfcdc548a7e8e7866b8384.tar.gz | |
skylake: set and clear wake masks in S0 <-> S0ix transitions
In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear the
wake masks when the SMI is invoked. For S0ix, EC sets and clears the
wake mask via this patch.
These functions are directly invoked from the state machine transition states.
During S0ix entry, the wake mask for lid open is enabled. During S0ix exit,
the wake mask for lid open is cleared. All pending events are also cleared
BRANCH=none
BUG=chrome-os-partner:48834
TEST=test lidopen in S0ix
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Change-Id: I52a15f502ef637f7b7e4b559820deecb831d818f
Reviewed-on: https://chromium-review.googlesource.com/320190
Commit-Ready: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lpc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/lpc.h b/include/lpc.h index c90a54a71c..3b77736f00 100644 --- a/include/lpc.h +++ b/include/lpc.h @@ -120,4 +120,7 @@ void lpc_disable_acpi_interrupts(void); /* Enable LPC ACPI interrupts */ void lpc_enable_acpi_interrupts(void); +void lpc_enable_wake_mask_for_lid_open(void); + +void lpc_disable_wake_mask_for_lid_open(void); #endif /* __CROS_EC_LPC_H */ |