diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2019-05-02 09:58:48 -0600 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-05-04 03:17:25 -0700 |
| commit | c1b08cd1b240332abfac339823a7468f52ff843d (patch) | |
| tree | 36dab0e83d126a10a34e046a1a017eced5d19ce4 /include | |
| parent | acb893a320f0398d25083a9ea102329c619845ab (diff) | |
| download | chrome-ec-c1b08cd1b240332abfac339823a7468f52ff843d.tar.gz | |
ish: preserve panic data across reset
This commit stores panic data across reset by storing panic data in
the last 256 bytes of AON memory (before AON ROM).
> crash divzero
========== PANIC ==========
Reason: Divide By Zero
Error Code = 0xFF00B60C
EIP = 0xFF010008
CS = 0x00010202
EFLAGS = 0x00103085
EAX = 0x00000001
EBX = 0xFF01B118
ECX = 0x00000000
EDX = 0x00000000
ESI = 0x00000000
EDI = 0xFF017E0E
Resetting system...
===========================
... ISH reset ...
> panicinfo
Saved panic data: (NEW)
Reason: Divide By Zero
Error Code = 0xFF00B60C
EIP = 0xFF010008
CS = 0x00010202
EFLAGS = 0x00103085
EAX = 0x00000001
EBX = 0xFF01B118
ECX = 0x00000000
EDX = 0x00000000
ESI = 0x00000000
EDI = 0xFF017E0E
BUG=b:129425206
BRANCH=none
TEST=see console output above (on arcada_ish)
Change-Id: I5c9e458b53076eafe7fa50ba851f2c6e863f2247
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1593418
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/config.h | 24 | ||||
| -rw-r--r-- | include/panic.h | 9 |
2 files changed, 26 insertions, 7 deletions
diff --git a/include/config.h b/include/config.h index 2a62f4f665..86f6447157 100644 --- a/include/config.h +++ b/include/config.h @@ -2609,6 +2609,13 @@ /* Support One Time Protection structure */ #undef CONFIG_OTP +/* + * Address to store persistent panic data at. By default, this will be + * at the end of RAM, and have a size of sizeof(struct panic_data) + */ +#undef CONFIG_PANIC_DATA_BASE +#undef CONFIG_PANIC_DATA_SIZE + /* Support PECI interface to x86 processor */ #undef CONFIG_PECI @@ -4073,6 +4080,23 @@ /******************************************************************************/ /* + * Store panic data at end of memory by default, unless otherwise + * configured. This is safe because we don't context switch away from + * the panic handler before rebooting, and stacks and data start at + * the beginning of RAM. + */ +#ifndef CONFIG_PANIC_DATA_SIZE +#define CONFIG_PANIC_DATA_SIZE sizeof(struct panic_data) +#endif + +#ifndef CONFIG_PANIC_DATA_BASE +#define CONFIG_PANIC_DATA_BASE (CONFIG_RAM_BASE \ + + CONFIG_RAM_SIZE \ + - CONFIG_PANIC_DATA_SIZE) +#endif + +/******************************************************************************/ +/* * Set minimum shared memory size, unless it is defined in board file. */ #ifndef CONFIG_SHAREDMEM_MINIMUM_SIZE diff --git a/include/panic.h b/include/panic.h index 45fc31583d..f3bccd18a0 100644 --- a/include/panic.h +++ b/include/panic.h @@ -89,13 +89,8 @@ enum panic_arch { PANIC_ARCH_X86 = 3, /* Intel x86 */ }; -/* - * Panic data goes at the end of RAM. This is safe because we don't context - * switch away from the panic handler before rebooting, and stacks and data - * start at the beginning of RAM. - */ -#define PANIC_DATA_PTR ((struct panic_data *)\ - (CONFIG_RAM_BASE + CONFIG_RAM_SIZE - sizeof(struct panic_data))) +/* Use PANIC_DATA_PTR to refer to the persistent storage location */ +#define PANIC_DATA_PTR ((struct panic_data *)CONFIG_PANIC_DATA_BASE) /* Flags for panic_data.flags */ /* panic_data.frame is valid */ |