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| author | Nicolas Boichat <drinkcat@chromium.org> | 2018-06-07 16:47:26 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-14 05:38:39 -0700 |
| commit | 24153748b61b9f771c3b4e4646b9f54b4e4e2a18 (patch) | |
| tree | 62f82a18f8226104d10d49872eed0c8f23e7f773 /include | |
| parent | b4f69d8a0cf5c4bc55880befe7cd995b1ddd2926 (diff) | |
| download | chrome-ec-24153748b61b9f771c3b4e4646b9f54b4e4e2a18.tar.gz | |
power/mt8183: Power sequencing logic for MT8183
MT8183 uses a power sequencing inspired from RK3399, with fewer
signals.
We only have 1 signal from PMIC (PMIC_PWR_GOOD), active in S0/S3,
and 1 signal from AP (AP_IN_S3_L), active in S3/S5.
One particularity of this design is that we need to reboot the EC
to RO on every single cold boot/reboot.
For the forced transition to S5, we assert the WATCHDOG signal
to PMIC to shut it down, which should usually work, if the PMIC
was configured properly by AP. If not, we also assert power+home
key (PMIC_EN_ODL) until the PMIC shuts down for good.
BRANCH=none
BUG=b:109850749
TEST=make BOARD=kukui -j
Change-Id: Ibcde8b937d7f4cecb0f470b9a7e0809fc24efae6
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1092402
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/config.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/config.h b/include/config.h index bb6b8bf8be..b51cbfc5b8 100644 --- a/include/config.h +++ b/include/config.h @@ -765,6 +765,7 @@ #undef CONFIG_CHIPSET_ECDRIVEN /* Dummy power module */ #undef CONFIG_CHIPSET_GEMINILAKE /* Intel Geminilake (x86) */ #undef CONFIG_CHIPSET_MT817X /* MediaTek MT817x */ +#undef CONFIG_CHIPSET_MT8183 /* MediaTek MT8183 */ #undef CONFIG_CHIPSET_RK3288 /* Rockchip rk3288 */ #undef CONFIG_CHIPSET_RK3399 /* Rockchip rk3399 */ #undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */ |