diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-05-05 14:14:43 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-12 02:50:09 +0000 |
| commit | a394302e4aef0349c30cbccf6b4623bcb3dda5bf (patch) | |
| tree | dbe5031332d6dc5c423cefcf3efabecb46bd42f4 /include | |
| parent | 1f09bd7c469fdede4f72425911b0a9d15a439c00 (diff) | |
| download | chrome-ec-a394302e4aef0349c30cbccf6b4623bcb3dda5bf.tar.gz | |
power: skylake: Add support for skylake power sequencing
Add power sequencing for Skylake, following the IMVP8 / ROP PMIC design
for SKL-U / SKL-Y.
BUG=chrome-os-partner:39510
TEST=Compile only
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ibf6a0e4415544b6b4b2cf28c167106ce4bfdc54e
Reviewed-on: https://chromium-review.googlesource.com/269460
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/config.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/config.h b/include/config.h index 47370d8aac..27137fdf00 100644 --- a/include/config.h +++ b/include/config.h @@ -317,12 +317,13 @@ /* AP chipset support; pick at most one */ #undef CONFIG_CHIPSET_BAYTRAIL /* Intel Bay Trail (x86) */ +#undef CONFIG_CHIPSET_BRASWELL /* Intel Braswell (x86) */ #undef CONFIG_CHIPSET_GAIA /* Gaia and Ares (ARM) */ #undef CONFIG_CHIPSET_HASWELL /* Intel Haswell (x86) */ #undef CONFIG_CHIPSET_IVYBRIDGE /* Intel Ivy Bridge (x86) */ #undef CONFIG_CHIPSET_ROCKCHIP /* Rockchip rk32xx */ +#undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */ #undef CONFIG_CHIPSET_TEGRA /* nVidia Tegra 5 */ -#undef CONFIG_CHIPSET_BRASWELL /* Intel Braswell (x86) */ /* Support chipset throttling */ #undef CONFIG_CHIPSET_CAN_THROTTLE |