diff options
author | Keith Short <keithshort@chromium.org> | 2020-07-19 16:23:23 -0600 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-08-13 14:26:53 +0000 |
commit | e0bf946ced052fe5e857b42da666ba252b03da95 (patch) | |
tree | d5218c56b92ecf3e27e62af0a19c8e9d34443134 /include | |
parent | 8ce0c16cc2d153b0002fbea64d08c09d98c3835f (diff) | |
download | chrome-ec-e0bf946ced052fe5e857b42da666ba252b03da95.tar.gz |
npcx: add support for rom resident sections
EC images are copied in full from flash to RAM. When the code RAM size
is smaller than 1/2 the flash size, the EC image size is limited to the
code RAM size, leaving unused flash space.
Create a new linker section .init_rom used to store data objects that
are single use in the previously unused flash area. Data objects can be
used at runtime by copying into RAM using the flash_read() function.
This change is tied to the NPCX flash layout, with asserts to ensure
builds fail if the CONFIG_CHIP_INIT_ROM_REGION is not supported by
the chip.
CLs that enable CONFIG_CHIP_INIT_ROM_REGION should not be merged until
the predecessor CL:2325764 is available in CPFE images.
BUG=b:160330682
BRANCH=none
TEST=make buildall
TEST=With debug code, use the _init_rom macro and validate the data can
be read using flash_read().
TEST=Using hex editor, verify .init_rom section located at 192K boundary
and unused bytes are filled with 0xFF.
TEST=compare_build.sh passes when run against waddledoo (npcx, cortex-m)
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: Ia0785798fd1938ad6a1c254a070b219027ee82a3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311268
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/common.h | 13 | ||||
-rw-r--r-- | include/config.h | 58 |
2 files changed, 71 insertions, 0 deletions
diff --git a/include/common.h b/include/common.h index c9a61545e6..92731182dc 100644 --- a/include/common.h +++ b/include/common.h @@ -111,6 +111,19 @@ #define __bss_slow __attribute__((section(".bss.slow"))) #endif +/* + * Place a read-only object into a ROM resident section. If supported by the + * EC chip, the object is part of the flash image but not copied into RAM + * automatically. Users may only access the data using the include/init_rom.h + * module. + * + * Requires CONFIG_CHIP_INIT_ROM_REGION is defined, otherwise the object is + * linked into the .rodata section. + */ +#ifndef __init_rom +#define __init_rom __attribute__((section(".init.rom"))) +#endif + /* gcc does not support __has_feature */ #ifndef __has_feature #define __has_feature(x) 0 diff --git a/include/config.h b/include/config.h index aa8ead6ba1..f80eac0513 100644 --- a/include/config.h +++ b/include/config.h @@ -1091,6 +1091,18 @@ */ #undef CONFIG_CHIP_UNCACHED_REGION +/* + * When defined, adds a new linker section to store objects that remain resident + * in ROM/flash. This is useful on ECs that execute all code from RAM and + * in which the RAM size is smaller than the flash size. + * + * Code can force objects into the .init_rom resident section using the + * __init_rom macro. Objects should accessed using the include/init_rom.h + * module. + */ +#undef CONFIG_CHIP_INIT_ROM_REGION + + /*****************************************************************************/ /* Chipset config */ @@ -1817,6 +1829,24 @@ #undef CONFIG_RW_SIZE /* + * Offset relative to CONFIG_EC_PROTECTED_STORAGE_OFF + * These define a region of flash used to store ROM resident data objects + * for RO images. This is only possible when the program memory is smaller + * than CONFIG_EC_PROTECTED_STORAGE_SIZE. + */ +#undef CONFIG_RO_ROM_RESIDENT_MEM_OFF +#undef CONFIG_RO_ROM_RESIDENT_SIZE + +/* + * Offset relative to CONFIG_EC_WRITABLE_STORAGE_OFF + * These define a region of flash used to store ROM resident data objects + * for RW images. This is only possible when the program memory is smaller + * than CONFIG_EC_WRITABLE_STORAGE_SIZE. + */ +#undef CONFIG_RW_ROM_RESIDENT_MEM_OFF +#undef CONFIG_RW_ROM_RESIDENT_SIZE + +/* * NPCX-specific bootheader geometry. * TODO(crosbug.com/p/23796): Factor these CONFIGs out. */ @@ -5347,6 +5377,34 @@ #define CONFIG_USB_PD_TBT_GEN3_CAPABLE #endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */ +/* + * CONFIG_CHIP_INIT_ROM_REGION requires that the chip has defined a + * ROM resident region to store the .init_rom section. + * + * These sections must also not be zero bytes, which will happen if + * the program size is the same as the flash size. + */ +#ifdef CONFIG_CHIP_INIT_ROM_REGION + +#ifndef CONFIG_RO_ROM_RESIDENT_SIZE +#error CONFIG_CHIP_INIT_ROM_REGION requires CONFIG_RO_ROM_RESIDENT_SIZE +#endif + +#ifndef CONFIG_RW_ROM_RESIDENT_SIZE +#error CONFIG_CHIP_INIT_ROM_REGION requires CONFIG_RW_ROM_RESIDENT_SIZE +#endif + + +#if (CONFIG_RO_ROM_RESIDENT_SIZE == 0) +#error CONFIG_RO_ROM_RESIDENT_SIZE is 0 with CONFIG_CHIP_INIT_ROM_REGION defined +#endif + +#if (CONFIG_RW_ROM_RESIDENT_SIZE == 0) +#error CONFIG_RW_ROM_RESIDENT_SIZE is 0 with CONFIG_CHIP_INIT_ROM_REGION defined +#endif + +#endif /* CONFIG_CHIP_INIT_ROM_REGION */ + /*****************************************************************************/ /* |