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| author | Zhuohao Lee <zhuohao@chromium.org> | 2022-04-11 18:06:40 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-04-21 09:51:18 +0000 |
| commit | bf6f0c21d951f00574d24e34040351e94d4545a0 (patch) | |
| tree | a2c9a153242a40b65d9db894857b16d8b8ced149 /include | |
| parent | 5efd8eea4be5dd1417e8e98b4f8fb5e9444cc169 (diff) | |
| download | chrome-ec-bf6f0c21d951f00574d24e34040351e94d4545a0.tar.gz | |
power/intel_x86: block RSMRST until the system is in S5
When we set the EN_S5_RAILS to enable the 3.3v/5v power for the ap
spi flash programming via the C2D2, the power sequence ic will
deassert the SEQ_EC_RSMRST_ODL in the G3 state. In order to avoid
the ap being powered on during the C2D2 programming, we need to
bypass the RSMRST before the system enters the S5. As a result,
we add CONFIG_CHIPSET_X86_RSMRST_AFTER_S5 to block the RSMRST
until the system goes to S5.
Since the APL/GLK already applied the same approach, we enable
the CONFIG_CHIPSET_X86_RSMRST_AFTER_S5 for the APL/GLK by default
in the config.h.
BUG=b:223084533
BRANCH=None
TEST=cros ap flash -b brya -i ${IMAGE}
Change-Id: I14039b405adc62e91436759eddacf6f9dc141eff
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3583905
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/config.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/config.h b/include/config.h index af8d75d382..eaf6dd0b7a 100644 --- a/include/config.h +++ b/include/config.h @@ -1465,6 +1465,9 @@ */ #undef CONFIG_CHIPSET_X86_RSMRST_DELAY +/* Passthrough RSMRST_L de-assertion after S5 */ +#undef CONFIG_CHIPSET_X86_RSMRST_AFTER_S5 + /* Support PMIC reset(using LDO_EN) in chipset */ #undef CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET @@ -6321,6 +6324,7 @@ #if defined(CONFIG_CHIPSET_APL_GLK) #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK +#define CONFIG_CHIPSET_X86_RSMRST_AFTER_S5 #endif #if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) || \ |