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| author | Philip Chen <philipchen@google.com> | 2017-09-22 14:29:40 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-10-11 13:19:33 -0700 |
| commit | 982f2bbfab02400cb09b7d7102db3285c1723762 (patch) | |
| tree | 1d7e9b38c83b7a54710c61028df3dcaf70a5791d /include | |
| parent | df12bc1c0246ceec39f28151efadb73f8e5fd7a5 (diff) | |
| download | chrome-ec-982f2bbfab02400cb09b7d7102db3285c1723762.tar.gz | |
chip/stm32/clock: Optionally use LSE as RTCCLK
The default RTCCLK comes from LSI, which can vary from 30kHz to 60kHz.
To use stm32 RTC for applications requiring accurate timing, let's setup
LSE (a more accurate clock source) as RTCCLK.
Also fix a typo in register.h as 'BCDR' should be 'BDCR' globally.
BUG=b:63908519
BRANCH=none
TEST=boot scarlet rev1 and wait for an hour,
confirm rtc time == kernel system time.
Change-Id: If4728bdd3b6384316e5337004a49c172eaec869d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/679601
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/config.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/config.h b/include/config.h index 86dacbe74f..f60766d165 100644 --- a/include/config.h +++ b/include/config.h @@ -668,6 +668,9 @@ /* Indicate if a clock source is connected to stm32f4's "HSE" specific input */ #undef CONFIG_STM32_CLOCK_HSE_HZ +/* Indicate if a clock source is connected to "LSE" specific input */ +#undef CONFIG_STM32_CLOCK_LSE + /* * Chip config for clock source * define = external crystal oscillator / undef = internal clock source |