intel_x86: Handle RSMRST signal in Intel x86 common code

BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
     Reef can boot to OS. S3, S5, hibernate are working.

Change-Id: Iddd16cba5f1dc62341dfbc8568b490439b7d593b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/427018
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 1 insertions, 23 deletions

diff --git a/power/apollolake.c b/power/apollolake.c
index 43e4360ba2..c3ca7f55f5 100644
--- a/power/apollolake.c
+++ b/power/apollolake.c
@@ -63,28 +63,6 @@ void chipset_reset(int cold_reset)
 	}
 }
 
-void handle_rsmrst(enum power_state state)
-{
-	/*
-	 * Pass through asynchronously, as SOC may not react
-	 * immediately to power changes.
-	 */
-	int in_level = gpio_get_level(GPIO_RSMRST_L_PGOOD);
-	int out_level = gpio_get_level(GPIO_PCH_RSMRST_L);
-
-	/* Nothing to do. */
-	if (in_level == out_level)
-		return;
-
-	/* Only passthrough RSMRST_L de-assertion on power up */
-	if (in_level && !power_s5_up)
-		return;
-
-	gpio_set_level(GPIO_PCH_RSMRST_L, in_level);
-
-	CPRINTS("Pass through GPIO_RSMRST_L_PGOOD: %d", in_level);
-}
-
 static void handle_all_sys_pgood(enum power_state state)
 {
 	/*
@@ -132,7 +110,7 @@ rsmrst_handle:
 	 * RSMRST_L is also checked in some states and, if asserted, will
 	 * force shutdown.
 	 */
-	handle_rsmrst(new_state);
+	common_intel_x86_handle_rsmrst(new_state);
 
 	return new_state;
 }