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author | Aaron Durbin <adurbin@chromium.org> | 2015-08-18 15:02:29 -0500 |
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committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-08-19 08:10:20 +0000 |
commit | b3d1171d42803d40e7a1f83375a1f3c69b1fbd07 (patch) | |
tree | 9273905441abb1e403e369d3669ce8603f35e75c /power/braswell.c | |
parent | 7ad94648a5fff9621cb106d7358f0e83c9539d20 (diff) | |
download | chrome-ec-b3d1171d42803d40e7a1f83375a1f3c69b1fbd07.tar.gz |
skylake: power sequencing update
There are a number issues with the current skylake power
sequencing. First, SLP_SUS_L was not being honored from
the chipset when a deep S5 or S3 was requested. Additionally
the BATLOW_L signal was being used to block the chipset from
waking which caused a race in waking from deep S5 that required
an additional pulse of the PCH_WAKE_L signal instead of the
chipset seeing the power button event. Another issue is that
POWER_S5 state was being completely bypassed so any global
resets that brought down SLP_S4_L caused the state machine
to enter into G3 state.
The code was changed to remove BATLOW_L usage, PCH_WAKE_L
in the POWER_G3S5 state, and SLP_SUS_L is honored in the
non POWER_S5G3 and POWER_G3 state. That allows SLP_SUS_L
pass-thru to work on glaods. Lastly the code was reorganized
to accomodate the above change without sprinkling them
throughout the state transitions.
BUG=chrome-os-partner:44081
BUG=chrome-os-partner:44082
BUG=chrome-os-partner:43475
BRANCH=None
TEST=Built and booted glados. Deep S3 and S5 wakes work. Fresh
flash plus a global reset doesn't bring the system down to G3.
Change-Id: Id1d7af1b6a733a9db5aad584950da8ab5898ea83
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293844
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'power/braswell.c')
0 files changed, 0 insertions, 0 deletions