diff options
| author | Kyoung Kim <kyoung.il.kim@intel.com> | 2015-06-18 17:03:40 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-15 03:39:29 +0000 |
| commit | 0a8c6c039641bc99433870738ae621aa0714d8f5 (patch) | |
| tree | 60bf474aa1d71907b06403c7011e841e900f2deb /power/braswell.c | |
| parent | 2a929afefbc0ec387545646b107309fea2fd82bb (diff) | |
| download | chrome-ec-0a8c6c039641bc99433870738ae621aa0714d8f5.tar.gz | |
Braswell: Add support for PMIC
Added support for PMIC in Braswell power sequencing code to support
the PMIC enabled Braswell devices.
BUG=none
TEST=Tested S3, S5, G3 & PG3 on BCRD2.
BRANCH=none
Change-Id: I247ef9506d0e8065c761bfb00b9141ec8ff5ada8
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283579
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'power/braswell.c')
| -rw-r--r-- | power/braswell.c | 33 |
1 files changed, 12 insertions, 21 deletions
diff --git a/power/braswell.c b/power/braswell.c index afd414da51..826ae7ab5a 100644 --- a/power/braswell.c +++ b/power/braswell.c @@ -142,7 +142,11 @@ enum power_state power_handle_state(enum power_state state) case POWER_G3S5: /* Exit SOC G3 */ +#ifdef CONFIG_PMIC + gpio_set_level(GPIO_PCH_SYS_PWROK, 1); +#else gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 0); +#endif CPRINTS("Exit SOC G3"); if (power_wait_signals(IN_PGOOD_S5)) { @@ -220,24 +224,6 @@ enum power_state power_handle_state(enum power_state state) /* Set SYS and CORE PWROK */ gpio_set_level(GPIO_PCH_SYS_PWROK, 1); - /* Wait 50 ms for platform reset to deassert */ - { - int i = 0; - CPRINTS("power wait for PLTRST# to deassert"); - while (lpc_get_pltrst_asserted()) { - usleep(MSEC); - - i++; - if (i >= 50) { - CPRINTS("power timeout on PLTRST#"); - chipset_force_shutdown(); - - /*wireless_set_state(WIRELESS_OFF);*/ - return POWER_S3; - } - } - } - return POWER_S0; @@ -249,8 +235,6 @@ enum power_state power_handle_state(enum power_state state) } if (!power_has_signals(IN_ALL_S0)) { - /* Power down to next state */ - gpio_set_level(GPIO_PCH_SYS_PWROK, 0); return POWER_S0S3; } @@ -259,9 +243,10 @@ enum power_state power_handle_state(enum power_state state) /* Call hooks before we remove power rails */ hook_notify(HOOK_CHIPSET_SUSPEND); +#ifndef CONFIG_PMIC /* Clear SYS and CORE PWROK */ gpio_set_level(GPIO_PCH_SYS_PWROK, 0); - +#endif /* Wait 40ns */ udelay(1); @@ -302,7 +287,13 @@ enum power_state power_handle_state(enum power_state state) gpio_config_module(MODULE_GPIO, 1); /* Enter SOC G3 */ +#ifdef CONFIG_PMIC + gpio_set_level(GPIO_PCH_SYS_PWROK, 0); + udelay(1); + gpio_set_level(GPIO_PCH_RSMRST_L, 0); +#else gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1); +#endif CPRINTS("Enter SOC G3"); return POWER_G3; |