diff options
| author | Aseda Aboagye <aaboagye@google.com> | 2017-07-25 11:33:15 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-07-25 20:08:32 -0700 |
| commit | 61a80d620ac5c332cf601f202200cd60ce13fb48 (patch) | |
| tree | 1548944e83d7fd0e21cc33069356c2aae1f18de7 /power/cannonlake.c | |
| parent | d483c289a91c84f8f2af3a8618383f5f738d02e1 (diff) | |
| download | chrome-ec-61a80d620ac5c332cf601f202200cd60ce13fb48.tar.gz | |
CNL: Use SYS_RST_L for warm/cold chipset reset.
The EC cannot control warm vs cold reset of the chipset using the
SYS_RST_L pin; it's just a reset request. This commit changes the
behaviour of chipset_reset to assert SYS_RST_L regardless if a cold or a
warm reset is requested.
BUG=b:63508740
BRANCH=None
TEST=make -j buildall; Flash a modified image on npcx7_evb, verify that
no panics or asserts are hit.
Change-Id: Idfd6f556bf909c7df4e8bd50a79b60719478cde7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/585573
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'power/cannonlake.c')
| -rw-r--r-- | power/cannonlake.c | 34 |
1 files changed, 18 insertions, 16 deletions
diff --git a/power/cannonlake.c b/power/cannonlake.c index 18a20ebef0..535010c103 100644 --- a/power/cannonlake.c +++ b/power/cannonlake.c @@ -53,26 +53,28 @@ void chipset_handle_espi_reset_assert(void) void chipset_reset(int cold_reset) { - CPRINTS("%s(%d)", __func__, cold_reset); - - if (cold_reset) { - if (gpio_get_level(GPIO_SYS_RESET_L) == 0) - return; - gpio_set_level(GPIO_SYS_RESET_L, 0); - /* Debounce time for SYS_RESET_L is 16 ms */ - udelay(20 * MSEC); - gpio_set_level(GPIO_SYS_RESET_L, 1); - } else { - /* Warm reset. */ - /* - * TODO(aaboagye): something about platform reset?? But we - * don't have that... - */ - } + /* + * The EC cannot control warm vs cold reset of the chipset using + * SYS_RESET_L; it's more of a request. + */ + CPRINTS("%s()", __func__); + + if (gpio_get_level(GPIO_SYS_RESET_L) == 0) + return; + + /* + * Debounce time for SYS_RESET_L is 16 ms. Wait twice that period to be + * safe. + */ + gpio_set_level(GPIO_SYS_RESET_L, 0); + udelay(32 * MSEC); + gpio_set_level(GPIO_SYS_RESET_L, 1); } enum power_state chipset_force_g3(void) { + chipset_force_shutdown(); + CPRINTS("Faking G3. (NOOP for now.)"); /* TODO(aaboagye): Do the right thing for real. */ /* TODO(aaboagye): maybe turn off DSW load switch. */ |