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| author | Aseda Aboagye <aaboagye@google.com> | 2017-10-16 16:03:24 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-10-23 04:28:23 -0700 |
| commit | b6733343abb6d9b7ce7446b94f312dab51d46fac (patch) | |
| tree | d54387e14251c5285e09225658e79a8822a42554 /power/cannonlake.c | |
| parent | 8d639f58ea58c851eb226af9fe676693fbc901f8 (diff) | |
| download | chrome-ec-b6733343abb6d9b7ce7446b94f312dab51d46fac.tar.gz | |
power: Add task-safe API to control 5V rail.
For certain cannonlake designs, the 5V rail can be controlled by both
the chipset task as well as other tasks such as the USB charger tasks to
perform BC1.2 detection. This commit introduces an API that allows the
tasks to enable/disable the 5V rail. Enable requests will immediately
enable the rail, however, attempting to disable the rail will only
result in a request. Once all tasks want to turn off the 5V rail, the
rail will be turned off.
A bitmask is introduced to keep track of the requests. Index 0 is for
the chipset task.
All of this is gated behind a config option:
CONFIG_POWER_PP5000_CONTROL
BUG=b:65991615
BRANCH=None
TEST=With other zoombini code, verify that 5V can be enabled and disabled.
Change-Id: I1722b4a272c4d6ee24408929f5a7402051bb9cf3
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/722322
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'power/cannonlake.c')
| -rw-r--r-- | power/cannonlake.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/power/cannonlake.c b/power/cannonlake.c index 535010c103..270eba5f35 100644 --- a/power/cannonlake.c +++ b/power/cannonlake.c @@ -12,6 +12,7 @@ #include "intel_x86.h" #include "power.h" #include "power_button.h" +#include "task.h" #include "timer.h" /* Console output macros */ @@ -104,11 +105,19 @@ enum power_state power_handle_state(enum power_state state) * In S3, enable 5V rail. Wireless rails are handled by common * x86 chipset code. */ +#ifdef CONFIG_POWER_PP5000_CONTROL + power_5v_enable(task_get_current(), 1); +#else gpio_set_level(GPIO_EN_PP5000, 1); +#endif break; case POWER_S3S5: +#ifdef CONFIG_POWER_PP5000_CONTROL + power_5v_enable(task_get_current(), 0); +#else gpio_set_level(GPIO_EN_PP5000, 0); +#endif break; default: |