power: Add Cannonlake chipset support.

BUG=b:63508740
BRANCH=None
TEST=`make -j buildall`

Change-Id: I66e0e229c61c85af8f1f1c263e107e9990399e6a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/564798
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

1 files changed, 118 insertions, 0 deletions

diff --git a/power/cannonlake.c b/power/cannonlake.c
new file mode 100644
index 0000000000..49a38051c3
--- /dev/null
+++ b/power/cannonlake.c
@@ -0,0 +1,118 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Cannonlake chipset power control module for Chrome EC */
+
+#include "cannonlake.h"
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "intel_x86.h"
+#include "power.h"
+#include "power_button.h"
+#include "timer.h"
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+
+static int forcing_shutdown;  /* Forced shutdown in progress? */
+
+void chipset_force_shutdown(void)
+{
+	CPRINTS("%s()", __func__);
+
+	/*
+	 * Force off. Sending a reset command to the PMIC will power off
+	 * the EC, so simulate a long power button press instead. This
+	 * condition will reset once the state machine transitions to G3.
+	 * Consider reducing the latency here by changing the power off
+	 * hold time on the PMIC.
+	 */
+	if (!chipset_in_state(CHIPSET_STATE_HARD_OFF)) {
+		forcing_shutdown = 1;
+		power_button_pch_press();
+	}
+}
+
+void chipset_handle_espi_reset_assert(void)
+{
+	/*
+	 * If eSPI_Reset# pin is asserted without SLP_SUS# being asserted, then
+	 * it means that there is an unexpected power loss (global reset
+	 * event). In this case, check if shutdown was being forced by pressing
+	 * power button. If yes, release power button.
+	 */
+	if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
+		forcing_shutdown) {
+		power_button_pch_release();
+		forcing_shutdown = 0;
+	}
+}
+
+void chipset_reset(int cold_reset)
+{
+	CPRINTS("%s(%d)", __func__, cold_reset);
+
+	if (cold_reset) {
+		if (gpio_get_level(GPIO_SYS_RESET_L) == 0)
+			return;
+		gpio_set_level(GPIO_SYS_RESET_L, 0);
+		/* Debounce time for SYS_RESET_L is 16 ms */
+		udelay(20 * MSEC);
+		gpio_set_level(GPIO_SYS_RESET_L, 1);
+	} else {
+		/* Warm reset. */
+		/*
+		 * TODO(aaboagye): something about platform reset??  But we
+		 * don't have that...
+		 */
+	}
+}
+
+enum power_state chipset_force_g3(void)
+{
+	CPRINTS("Faking G3.  (NOOP for now.)");
+	/* TODO(aaboagye): Do the right thing for real. */
+	return POWER_G3;
+}
+
+enum power_state power_handle_state(enum power_state state)
+{
+	enum power_state new_state;
+	int dswpwrok_in = gpio_get_level(GPIO_PMIC_DPWROK);
+
+	/* Pass-through DSW_PWROK to CNL. */
+	gpio_set_level(GPIO_PCH_DSW_PWROK, dswpwrok_in);
+	CPRINTS("Pass thru GPIO_DSW_PWROK: %d", dswpwrok_in);
+
+	common_intel_x86_handle_rsmrst(state);
+
+	if (state == POWER_S5 && forcing_shutdown) {
+		power_button_pch_release();
+		forcing_shutdown = 0;
+	}
+
+	/* TODO(aaboagye): Enable 3300_DSW in Deep Sx only. */
+	switch (state) {
+	case POWER_S5S3:
+		/*
+		 * In S3, enable 5V rail.  Wireless rails are handled by common
+		 * x86 chipset code.
+		 */
+		gpio_set_level(GPIO_EN_PP5000, 1);
+		break;
+
+	case POWER_S3S5:
+		gpio_set_level(GPIO_EN_PP5000, 0);
+		break;
+
+	default:
+		break;
+	};
+
+	new_state = common_intel_x86_power_handle_state(state);
+
+	return new_state;
+}