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| author | Scott Collyer <scollyer@google.com> | 2018-08-16 19:12:06 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-05 01:25:52 -0700 |
| commit | 6ea513b952302ad70f1cc6efd0b02c1e550c1c0a (patch) | |
| tree | 7baf6c6ff1f56bc86604dfdbe61a428528247181 /power/icelake.c | |
| parent | c8df8cd58bb4d0bdbf3f953e4a4394dec797609f (diff) | |
| download | chrome-ec-6ea513b952302ad70f1cc6efd0b02c1e550c1c0a.tar.gz | |
ICL: Modify force_shutdown to meet PCH timing requirements
Time between RSMRST going low and the _A rails dropping 5% must be >
400 ns. To meet this timing set the PCH pass through low at beginning
of chipset_force_shutdown. Similarly, set EC_PCH_DSW_PWROK low to meet
its timing requirement relative to _A rails dropping 5%.
BUG=b:112170058
BRANCH=none
TEST=Verified that timing meets the specifications.
Change-Id: I88573a4b926f5804d1a0df5702078eb32a6d0221
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1179142
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'power/icelake.c')
| -rw-r--r-- | power/icelake.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/power/icelake.c b/power/icelake.c index 4e7b829322..04b734c213 100644 --- a/power/icelake.c +++ b/power/icelake.c @@ -30,6 +30,12 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason) CPRINTS("%s()", __func__, reason); report_ap_reset(reason); + /* Turn off RMSRST_L to meet tPCH12 */ + gpio_set_level(GPIO_EC_PCH_RSMRST_L, 0); + + /* Turn off DSW_PWROK to meet tPCH14 */ + gpio_set_level(GPIO_EC_PCH_DSW_PWROK, 0); + /* Turn off DSW load switch. */ gpio_set_level(GPIO_EN_PP3300_A, 0); @@ -37,14 +43,15 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason) * TODO(b/111810925): Replace this wait with * power_wait_signals_timeout() */ - /* Now wait for DSW_PWROK to go away. */ - while (gpio_get_level(GPIO_PG_EC_DSW_PWROK) && (timeout_ms > 0)) { + /* Now wait for DSW_PWROK and RSMRST_ODL to go away. */ + while (gpio_get_level(GPIO_PG_EC_DSW_PWROK) && + gpio_get_level(GPIO_PG_EC_RSMRST_ODL) && (timeout_ms > 0)) { msleep(1); timeout_ms--; }; if (!timeout_ms) - CPRINTS("DSW_PWROK didn't go low! Assuming G3."); + CPRINTS("DSW_PWROK or RSMRST_ODL didn't go low! Assuming G3."); } void chipset_handle_espi_reset_assert(void) |