diff options
| author | Keith Short <keithshort@chromium.org> | 2020-03-04 12:53:25 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-09 00:56:31 +0000 |
| commit | 3b831bbf6ee24a09ef65064d7374e6ef7960eedf (patch) | |
| tree | 1e60e398e159b257a3cba56bc037844d0b289d84 /power/icelake.h | |
| parent | 4d39614441258dc5788c2a55000abe56ac43d3fe (diff) | |
| download | chrome-ec-3b831bbf6ee24a09ef65064d7374e6ef7960eedf.tar.gz | |
icelake: Cleanup power sequencing for IceLake/TigerLake/JasperLake
Configure PWROK generation related signals for Ice Lake, Tiger Lake, and
Jasper Lake SoCs. The array driven sequencing provides better
flexibility for the PWROK signals, some of which may be automatically
handled by the platform and some require EC control.
BUG=b:150726713
BRANCH=none
TEST=make buildall
TEST=Volteer: verify VCCIN enable and SYS_PWROK generation during S0 and
verify signals are deasserted when exiting S0.
TEST=Wadledoo: verified 2ms delay between ALL_SYS_PWRGD and PCH_PWROK,
verified JPL sequences to S0.
Change-Id: Iceae29c65398643839b31f6cd757352282849fda
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2088285
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'power/icelake.h')
| -rw-r--r-- | power/icelake.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/power/icelake.h b/power/icelake.h index c051a2516a..08c14718ec 100644 --- a/power/icelake.h +++ b/power/icelake.h @@ -8,6 +8,8 @@ #ifndef __CROS_EC_ICELAKE_H #define __CROS_EC_ICELAKE_H +#include "stdbool.h" + /* Input state flags. */ #define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) #define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) @@ -40,4 +42,41 @@ enum power_signal { POWER_SIGNAL_COUNT }; +struct intel_x86_pwrok_signal { + enum gpio_signal gpio; + bool active_low; + int delay_ms; +}; + +/* + * Ice Lake/Tiger Lake/Jasper Lake PWROK Generation + * + * The following signals are controlled based on the state of the ALL_SYS_PWRGD + * signal + * + * VCCIN enable (input to the VCCIN voltage rail controller) + * VCCST_PWRGD (input to the SoC) + * PCH_PWROK (input to the SoC) + * SYS_PWROK (input to the SoC) + * + * For any the above signals that are controlled by the EC, create an entry + * in the pwrok_signal_assert_list[] and pwrok_signal_deassert_list[] arrays. + * The typical order for asserting the signals is shown above, the deassert + * order is the reverse. + * + * ALL_SYS_PWRGD indicates when all the following are asserted. + * RSMRST_PWRGD & DPWROK + * S4 voltage rails good (DDR) + * VCCST voltage rail good + * S0 voltage rails good + * + * ALL_SYS_PWRGD can be implemented as a single GPIO if the platform power logic + * combines the above power good signals. Otherwise your board can override + * intel_x86_get_pg_ec_all_sys_pwrgd() to check multiple power good signals. + */ +extern const struct intel_x86_pwrok_signal pwrok_signal_assert_list[]; +extern const int pwrok_signal_assert_count; +extern const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[]; +extern const int pwrok_signal_deassert_count; + #endif /* __CROS_EC_ICELAKE_H */ |