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| author | Scott Collyer <scollyer@google.com> | 2018-07-04 09:13:41 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-07-27 19:11:09 -0700 |
| commit | be93944bf6900f5efb190340841d6dbeb3371c16 (patch) | |
| tree | 753aa54fc3ef98bf5b07730dab3613a8e75bfe01 /power/icelake.h | |
| parent | e7b3fe0a346cc3471555272e008cf95fc69a7925 (diff) | |
| download | chrome-ec-be93944bf6900f5efb190340841d6dbeb3371c16.tar.gz | |
icelake: Add power sequencing support for icelake
This CL adds code to support x86 power sequencing for icelake.
BRANCH=none
CQ-DEPEND=I0bf29d69de471c64f905ee8aa070b15b4f34f2ba
BUG=b:111121615,b:111853963
TEST=make buildall. Also tested on P0 and verified that AP gets to S0.
Change-Id: I3513f2e598162b2362d56c33df76d16b63864bd3
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1123318
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'power/icelake.h')
| -rw-r--r-- | power/icelake.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/power/icelake.h b/power/icelake.h new file mode 100644 index 0000000000..f28e1d71dd --- /dev/null +++ b/power/icelake.h @@ -0,0 +1,29 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Icelake chipset power control module for Chrome EC */ + +#ifndef __CROS_EC_ICELAKE_H +#define __CROS_EC_ICELAKE_H + +/* Input state flags. */ +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) + +#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ + IN_PCH_SLP_S4_DEASSERTED | \ + IN_PCH_SLP_SUS_DEASSERTED) + +#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK) + +#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED) + +#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED + +#define CHARGER_INITIALIZED_DELAY_MS 100 +#define CHARGER_INITIALIZED_TRIES 40 + +#endif /* __CROS_EC_ICELAKE_H */ |