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author | Daisuke Nojiri <dnojiri@chromium.org> | 2019-10-21 10:07:48 -0700 |
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committer | Commit Bot <commit-bot@chromium.org> | 2020-02-09 08:31:43 +0000 |
commit | 37151225f4d791204a75173eec64ebfdaf2cbdec (patch) | |
tree | a9680e1fd0897c1ea6e0461055760c42944fdee7 /power/intel_x86.c | |
parent | a4f7c8ef7c0b9b3206f67299414c2cbd2a5fe84a (diff) | |
download | chrome-ec-37151225f4d791204a75173eec64ebfdaf2cbdec.tar.gz |
EFS2: Implement Early Firmware Selection ver.2
EFS v1 allowed Chromeboxes to verify RW without AP. EFS v2 will bring
the benefts to Chromebooks, which are:
- Reduce RO dependency and presence. Allow more code to be updated
in the fields.
- Remove jumptag and workarounds needed for late sysjump.
Major imporvements over v1 are:
- No A/B slot required.
- No signature in RW or public key in RO.
- Rollback-attack protection.
- Verifies only RW being used instead of whole RW section.
For battery-equipped devices, additional benefts are:
- Immediate boot on drained battery.
- Support recovery mode regardless of battery condition.
- Faster charge in S5/G3.
EC-Cr50 communication is based on the shared UART (go/ec-cr50-comm).
EFS2 is documented in go/ec-efs2.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=chromium:1045217,chromium:141143112
BRANCH=none
TEST=Boot Helios in NORMAL/NO_BOOT/NO_BOOT_RECOVERY/RECOVERY mode.
TEST=Wake up EC from hibernate.
TEST=Make EC assert PACKET_MODE to wake up Cr50 from deepsleep.
Change-Id: I98a4fe1ecc59d106810a75daec3c424f953ff880
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015357
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'power/intel_x86.c')
-rw-r--r-- | power/intel_x86.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/power/intel_x86.c b/power/intel_x86.c index ecf36268cb..334a9367ca 100644 --- a/power/intel_x86.c +++ b/power/intel_x86.c @@ -737,7 +737,7 @@ enum ec_error_list intel_x86_wait_power_up_ok(void) power_up_inhibited = 0; #endif -#ifdef CONFIG_VBOOT_EFS +#if defined(CONFIG_VBOOT_EFS) || defined(CONFIG_VBOOT_EFS2) /* * We have to test power readiness here (instead of S5->S3) * because when entering S5, EC enables EC_ROP_SLP_SUS pin |