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author | Sugnan Prabhu S <sugnan.prabhu.s@intel.com> | 2022-02-02 20:25:08 +0530 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2022-03-09 17:05:55 +0000 |
commit | 5e2e973b4ef0cf02596bdfc5fa81e7f4e704f446 (patch) | |
tree | cd309aaa5f883c794500797e35e44f15ed9d6871 /power/intel_x86.c | |
parent | c79f4f71c787d3eb772b9d38f421b4be26780c96 (diff) | |
download | chrome-ec-5e2e973b4ef0cf02596bdfc5fa81e7f4e704f446.tar.gz |
intel_x86: Add config to configure S5 exit timer
On enabling Delayed Authentication Mode(DAM) in the coreboot for latest
platforms, system takes more time to exit from S5 than the current wait
time(4secs). Due to which EC forces the system to G3 after few retries.
This patch adds a new config to allow configuration of this timeout
value for which EC has to wait for S5 exit before performing RTC reset
and forcing the system to G3.
BRANCH=None
BUG=b:191742284
TEST=Boot test on Brya with the DAM enabled coreboot
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Change-Id: I78821280fa5928682c9c0c742a4e00299ac49db0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3432445
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com>
Diffstat (limited to 'power/intel_x86.c')
-rw-r--r-- | power/intel_x86.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/power/intel_x86.c b/power/intel_x86.c index e020874de6..9f26943dae 100644 --- a/power/intel_x86.c +++ b/power/intel_x86.c @@ -105,7 +105,8 @@ static enum power_state power_wait_s5_rtc_reset(void) while ((power_get_signals() & IN_PCH_SLP_S4_DEASSERTED) == 0) { /* Handle RSMRST passthru event while waiting */ common_intel_x86_handle_rsmrst(POWER_S5); - if (task_wait_event(SECOND*4) == TASK_EVENT_TIMER) { + if (task_wait_event(SECOND * CONFIG_S5_EXIT_WAIT) == + TASK_EVENT_TIMER) { CPRINTS("timeout waiting for S5 exit"); chipset_force_g3(); |