summaryrefslogtreecommitdiff
path: root/power/intel_x86.c
diff options
context:
space:
mode:
authorVincent Palatin <vpalatin@chromium.org>2018-03-02 11:26:00 +0100
committerchrome-bot <chrome-bot@chromium.org>2018-03-05 23:48:29 -0800
commit63c849a363e119b75693760262644148d145dd01 (patch)
tree545067be7a222ddb5c2e32b13ec651a5f1a4e999 /power/intel_x86.c
parentb42dd73603844c03b44d88a4513df330ee168496 (diff)
downloadchrome-ec-63c849a363e119b75693760262644148d145dd01.tar.gz
stm32: convert to CONFIG_CHIP_MEMORY_REGIONS
Remove the former special case for USB RAM Add additional RAM regions for STM32H7. For USB RAM, add an explicit alignment directive to ensure we always meet the 8-byte boundary hardware constraint for the BTABLE. This was already true because we put the .usb_ram.btable section first. I keep this property by alpha-sorting the sections but makes it more explicit by adding a 2-digit numeric prefix: e.g. 00_firstsection, 99_lastsection. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, along with the following CLs, run the firmware with large arrays in special AHB memory regions. TEST=build all targets with and without the patch and verify that all smap files are identical. Change-Id: I9ee7f519a13cb14ba9997220f22180028f9c0175 Reviewed-on: https://chromium-review.googlesource.com/946369 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'power/intel_x86.c')
0 files changed, 0 insertions, 0 deletions