diff options
author | Peter Marheine <pmarheine@chromium.org> | 2023-02-16 00:14:21 +0000 |
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committer | Peter Marheine <pmarheine@chromium.org> | 2023-02-16 00:14:21 +0000 |
commit | f43d6df6f2860dbe8ec15aebdc28890771ad7897 (patch) | |
tree | 6877eff7016f9979e46017ea5221a16d36344304 /power/mt8186.c | |
parent | dce247e97903a2464ff8884106bffa43587c1dcb (diff) | |
parent | 0849542c72359150a357945c010dca6b5a213633 (diff) | |
download | chrome-ec-f43d6df6f2860dbe8ec15aebdc28890771ad7897.tar.gz |
Merge remote-tracking branch cros/main into firmware-nissa-15217.B-mainfirmware-nissa-15217.126.B-main
Generated by: ./util/update_release_branch.py --zephyr --board nissa firmware-
nissa-15217.B-main
Relevant changes:
git log --oneline dce247e979..0849542c72 -- zephyr/program/nissa
util/getversion.sh
0849542c72 zephyr: add sleep property for keyboard factory test
5825d894b9 nissa: disable PLATFORM_EC_TCPC_INTERRUPT
25a400690f yavikso: Update fan table version 3
9263f14536 zephyr: remove shi node and add references to shi0
b40c6970d3 Craask: Charger limit for 65w adapter
6fd2d3ea6c zephyr: add comments for tcpc driver
00986ffb1c zephyr: move usbc interrupt handler to shim
2508094b14 yaviks: reduce RW image size (64KB)
55b6aaf52f yaviks: enable keyboard factory test
4786d1eac6 nissa: Add ocpc init function to Nissa boards
2ae1083638 zephyr: cros_kb: set KSI/KSO kbs mode by pinctrl driver
d415f4665a yaviks: Fix OCPC Vsys overshooting
93f9d42a7c zephyr: config: drop few more redundant options
BRANCH=None
BUG=b:254148652 b:260762509 b:265220075 b:268273712 b:265763662
BUG=b:253557900 b:254148652 b:269212593 b:267404783 b:262352202
TEST=`make -j buildall`
Force-Relevant-Builds: all
Change-Id: I195dd82af114180b611f9afd1465a69f7f43d417
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Diffstat (limited to 'power/mt8186.c')
-rw-r--r-- | power/mt8186.c | 36 |
1 files changed, 23 insertions, 13 deletions
diff --git a/power/mt8186.c b/power/mt8186.c index 00972e53a0..f4f91faa51 100644 --- a/power/mt8186.c +++ b/power/mt8186.c @@ -4,7 +4,7 @@ */ /* - * MT8186 SoC power sequencing module for Chrome EC + * MT8186/MT8188 SoC power sequencing module for Chrome EC * * This implements the following features: * @@ -22,7 +22,6 @@ */ #include "battery.h" -#include "builtin/assert.h" #include "chipset.h" #include "common.h" #include "gpio.h" @@ -55,6 +54,9 @@ #define POWERBTN_BOOT_DELAY (10 * MSEC) #define PMIC_EN_PULSE_MS 50 +/* PG4200 S5 ready delay */ +#define PG_PP4200_S5_DELAY (100 * MSEC) + /* Maximum time it should for PMIC to turn on after toggling PMIC_EN_ODL. */ #define PMIC_EN_TIMEOUT (300 * MSEC) @@ -68,17 +70,10 @@ #define NORMAL_SHUTDOWN_DELAY (150 * MSEC) #define RESET_FLAG_TIMEOUT (2 * SECOND) -#ifndef CONFIG_ZEPHYR -/* power signal list. Must match order of enum power_signal. */ -const struct power_signal_info power_signal_list[] = { - { GPIO_AP_EC_SYSRST_ODL, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_RST" }, - { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3" }, - { GPIO_AP_EC_WDTRST_L, POWER_SIGNAL_ACTIVE_LOW, "AP_WDT_ASSERTED" }, - { GPIO_AP_EC_WARM_RST_REQ, POWER_SIGNAL_ACTIVE_HIGH, - "AP_WARM_RST_REQ" }, -}; -BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); -#endif /* CONFIG_ZEPHYR */ +#if defined(CONFIG_PLATFORM_EC_POWERSEQ_MT8188) && \ + !DT_NODE_EXISTS(DT_NODELABEL(en_pp4200_s5)) +#error Must have dt node en_pp4200_s5 for MT8188 power sequence +#endif /* indicate MT8186 is processing a chipset reset. */ static bool is_resetting; @@ -360,6 +355,14 @@ enum power_state power_handle_state(enum power_state state) gpio_enable_interrupt(GPIO_AP_EC_WARM_RST_REQ); gpio_enable_interrupt(GPIO_AP_EC_WDTRST_L); +#if DT_NODE_EXISTS(DT_NODELABEL(en_pp4200_s5)) + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(en_pp4200_s5), 1); + + if (power_wait_mask_signals_timeout(PG_PP4200_S5, PG_PP4200_S5, + PG_PP4200_S5_DELAY)) + return POWER_S5G3; +#endif + GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 1); msleep(PMIC_EN_PULSE_MS); GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 0); @@ -447,9 +450,15 @@ enum power_state power_handle_state(enum power_state state) /* Call hooks before we remove power rails */ hook_notify(HOOK_CHIPSET_SHUTDOWN); +#if DT_NODE_EXISTS(DT_NODELABEL(en_pp4200_s5)) + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(en_pp4200_s5), 0); + + hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE); +#endif return POWER_S5; case POWER_S5G3: +#if !DT_NODE_EXISTS(DT_NODELABEL(en_pp4200_s5)) /* * Normally, this is called in S3S5, but if it's a shutdown * triggered by EC side, then EC is unable to set up PMIC @@ -459,6 +468,7 @@ enum power_state power_handle_state(enum power_state state) * will enter G3 after EC_PMIC_EN_ODL is released. */ hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE); +#endif return POWER_G3; default: CPRINTS("Unexpected power state %d", state); |