diff options
| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2017-01-10 17:35:36 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-01-21 10:03:45 -0800 |
| commit | 927b2e754f772965e2de285c5c7ab3dc191aba51 (patch) | |
| tree | 33193e64f32d6aae8bf94fa9ba32efdddc4cf58a /power/skylake.c | |
| parent | 44eb5829c6cc57e3448733abd2349de0cc562809 (diff) | |
| download | chrome-ec-927b2e754f772965e2de285c5c7ab3dc191aba51.tar.gz | |
intel_x86: Handle RSMRST signal in Intel x86 common code
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
Reef can boot to OS. S3, S5, hibernate are working.
Change-Id: Iddd16cba5f1dc62341dfbc8568b490439b7d593b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/427018
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'power/skylake.c')
| -rw-r--r-- | power/skylake.c | 30 |
1 files changed, 1 insertions, 29 deletions
diff --git a/power/skylake.c b/power/skylake.c index c821ecb268..2e5425a794 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -5,7 +5,6 @@ /* Skylake IMVP8 / ROP PMIC chipset power control module for Chrome EC */ -#include "board_config.h" #include "chipset.h" #include "console.h" #include "gpio.h" @@ -81,33 +80,6 @@ void chipset_reset(int cold_reset) } } -void handle_rsmrst(enum power_state state) -{ - /* - * Pass through RSMRST asynchronously, as PCH may not react - * immediately to power changes. - */ - int rsmrst_in = gpio_get_level(GPIO_RSMRST_L_PGOOD); - int rsmrst_out = gpio_get_level(GPIO_PCH_RSMRST_L); - - /* Nothing to do. */ - if (rsmrst_in == rsmrst_out) - return; - -#ifdef CONFIG_BOARD_HAS_BEFORE_RSMRST - board_before_rsmrst(rsmrst_in); -#endif - - /* - * Wait at least 10ms between power signals going high - * and deasserting RSMRST to PCH. - */ - if (rsmrst_in) - msleep(10); - gpio_set_level(GPIO_PCH_RSMRST_L, rsmrst_in); - CPRINTS("RSMRST: %d", rsmrst_in); -} - static void handle_slp_sus(enum power_state state) { /* If we're down or going down don't do anythin with SLP_SUS_L. */ @@ -123,7 +95,7 @@ enum power_state power_handle_state(enum power_state state) enum power_state new_state; /* Process RSMRST_L state changes. */ - handle_rsmrst(state); + common_intel_x86_handle_rsmrst(state); if (state == POWER_S5 && forcing_shutdown) { power_button_pch_release(); |