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| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2016-11-02 11:04:47 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-01-20 22:40:32 -0800 |
| commit | 8e4d4291726831cc35b3991418331db9a247a98b (patch) | |
| tree | 817dcf27c29cc9946c2af92119302cecb0484667 /power/skylake.h | |
| parent | 2b54aa9a9b061117021eff22385c9de474ab090b (diff) | |
| download | chrome-ec-8e4d4291726831cc35b3991418331db9a247a98b.tar.gz | |
power: Group Intel x86 power sequencing common code
Grouping the Intel x86 power sequencing common code so that
the future chipset power sequencing implementation can make
use of the existing code.
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
Manually tested on Reef & Chell.
System can boot to OS. S3, S5, hibernate are working.
Change-Id: I29dc208eacb3db47c640d028e9551ab3d8d4288c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/402272
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'power/skylake.h')
| -rw-r--r-- | power/skylake.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/power/skylake.h b/power/skylake.h index d44fb00e19..2a6f8fc4e7 100644 --- a/power/skylake.h +++ b/power/skylake.h @@ -28,6 +28,8 @@ #define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED) +#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED + #define CHARGER_INITIALIZED_DELAY_MS 100 #define CHARGER_INITIALIZED_TRIES 40 |