diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-06-27 15:18:23 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-28 07:41:05 +0000 |
| commit | ed44112c8e161a724eebd1b3c934a4af3f5ce11f (patch) | |
| tree | faeb5674a45b42d2b5bb9979ea0c9acf405013c5 /power | |
| parent | a6b92b8e7a1e5cdc50317a9e2d5f689923ab51a5 (diff) | |
| download | chrome-ec-ed44112c8e161a724eebd1b3c934a4af3f5ce11f.tar.gz | |
power/alderlake_slg4bd44540.c: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: I6ce0327ee2bb3085c4f4cabe06cbf2beb566c2ba
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730460
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/alderlake_slg4bd44540.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/power/alderlake_slg4bd44540.c b/power/alderlake_slg4bd44540.c index 0f7b5cb3e4..0f2bd18d60 100644 --- a/power/alderlake_slg4bd44540.c +++ b/power/alderlake_slg4bd44540.c @@ -24,30 +24,29 @@ */ /* PG_EC_ALL_SYS_PWRGD high to VCCST_PWRGD high delay */ -#define VCCST_PWRGD_DELAY_MS 2 +#define VCCST_PWRGD_DELAY_MS 2 /* IMVP9_VRRDY high to PCH_PWROK high delay */ -#define PCH_PWROK_DELAY_MS 2 +#define PCH_PWROK_DELAY_MS 2 /* PG_EC_ALL_SYS_PWRGD high to EC_PCH_SYS_PWROK high delay */ -#define SYS_PWROK_DELAY_MS 45 +#define SYS_PWROK_DELAY_MS 45 /* IMVP9_VRRDY high timeout */ -#define VRRDY_TIMEOUT_MS 50 +#define VRRDY_TIMEOUT_MS 50 /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) #ifdef CONFIG_BRINGUP #define GPIO_SET_LEVEL(signal, value) \ gpio_set_level_verbose(CC_CHIPSET, signal, value) #else -#define GPIO_SET_LEVEL(signal, value) \ - gpio_set_level(signal, value) +#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value) #endif /* The wait time is ~150 msec, allow for safety margin. */ -#define IN_PCH_SLP_SUS_WAIT_TIME_USEC (250 * MSEC) +#define IN_PCH_SLP_SUS_WAIT_TIME_USEC (250 * MSEC) /* Power signals list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { @@ -250,7 +249,6 @@ enum power_state power_handle_state(enum power_state state) common_intel_x86_handle_rsmrst(state); switch (state) { - case POWER_G3S5: GPIO_SET_LEVEL(GPIO_EN_S5_RAILS, 1); @@ -262,7 +260,8 @@ enum power_state power_handle_state(enum power_state state) * signal doesn't go high within 250 msec then go back to G3. */ if (power_wait_signals_timeout(IN_PCH_SLP_SUS_DEASSERTED, - IN_PCH_SLP_SUS_WAIT_TIME_USEC) != EC_SUCCESS) { + IN_PCH_SLP_SUS_WAIT_TIME_USEC) != + EC_SUCCESS) { CPRINTS("SLP_SUS_L didn't go high! Going back to G3."); return POWER_S5G3; } |