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| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-06-27 15:18:54 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-28 08:39:18 +0000 |
| commit | 596255f515af59b7ca78864b70849d1bc0ca99e4 (patch) | |
| tree | 064e49964005ac8d19b587ac2263df661ac26726 /power | |
| parent | c31bbaeac2b16f855df2f300c27cbe26ffd1d1c8 (diff) | |
| download | chrome-ec-596255f515af59b7ca78864b70849d1bc0ca99e4.tar.gz | |
power/meteorlake.c: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: I55993b8007f621b6a78398b863199fb90b1832a7
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727062
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/meteorlake.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/power/meteorlake.c b/power/meteorlake.c index 80785c2345..9a92768ad3 100644 --- a/power/meteorlake.c +++ b/power/meteorlake.c @@ -20,14 +20,13 @@ #include "timer.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) #ifdef CONFIG_BRINGUP #define GPIO_SET_LEVEL(signal, value) \ gpio_set_level_verbose(CC_CHIPSET, signal, value) #else -#define GPIO_SET_LEVEL(signal, value) \ - gpio_set_level(signal, value) +#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value) #endif /* Power signals list. Must match order of enum power_signal. */ @@ -117,7 +116,6 @@ static void enable_pp5000_rail(void) power_5v_enable(task_get_current(), 1); else GPIO_SET_LEVEL(GPIO_EN_PP5000, 1); - } /* @@ -126,7 +124,7 @@ static void enable_pp5000_rail(void) * ¶m level 0 deasserts the signal, other values assert the signal */ static void pwrok_signal_set(const struct intel_x86_pwrok_signal *signal, - int level) + int level) { GPIO_SET_LEVEL(signal->gpio, signal->active_low ? !level : level); } @@ -167,8 +165,9 @@ static void all_sys_pwrgd_pass_thru(void) } /* PCH_PWROK is combination of ALL_SYS_PWRGD and SLP_S3 */ - gpio_set_level(GPIO_PCH_PWROK, all_sys_pwrgd_in && - power_signal_get_level(SLP_S3_SIGNAL_L)); + gpio_set_level(GPIO_PCH_PWROK, + all_sys_pwrgd_in && + power_signal_get_level(SLP_S3_SIGNAL_L)); } enum power_state power_handle_state(enum power_state state) @@ -178,7 +177,6 @@ enum power_state power_handle_state(enum power_state state) common_intel_x86_handle_rsmrst(state); switch (state) { - case POWER_G3S5: if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)) { /* |