ec: delete auron and rambi boards

These boards have been succeeded by newer boards.

BUG=chromium:686106
TEST=make -j buildall
CQ-DEPEND=CL:434909
BRANCH=none

Change-Id: I2c964c1fdd7f8bbc5dab07caa88864847ba4e312
Reviewed-on: https://chromium-review.googlesource.com/434540
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>

3 files changed, 0 insertions, 805 deletions

diff --git a/power/baytrail.c b/power/baytrail.c
deleted file mode 100644
index 975d9d27d8..0000000000
--- a/power/baytrail.c
+++ /dev/null
@@ -1,425 +0,0 @@
-/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* X86 baytrail chipset power control module for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "lpc.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "util.h"
-#include "wireless.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Input state flags */
-#define IN_PGOOD_PP5000            POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
-#define IN_PGOOD_PP1050            POWER_SIGNAL_MASK(X86_PGOOD_PP1050)
-#define IN_PGOOD_S5                POWER_SIGNAL_MASK(X86_PGOOD_S5)
-#define IN_PGOOD_VCORE             POWER_SIGNAL_MASK(X86_PGOOD_VCORE)
-#define IN_SLP_S3_DEASSERTED       POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_SLP_S4_DEASSERTED       POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-
-/* All always-on supplies */
-#define IN_PGOOD_ALWAYS_ON   (IN_PGOOD_S5)
-/* All non-core power rails */
-#define IN_PGOOD_ALL_NONCORE (IN_PGOOD_PP5000)
-/* All core power rails */
-#define IN_PGOOD_ALL_CORE    (IN_PGOOD_VCORE)
-/* Rails required for S3 */
-#define IN_PGOOD_S3          (IN_PGOOD_ALWAYS_ON)
-/* Rails required for S0 */
-#define IN_PGOOD_S0          (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE)
-
-/* All PM_SLP signals from PCH deasserted */
-#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_DEASSERTED | IN_SLP_S4_DEASSERTED)
-/* All inputs in the right state for S0 */
-#define IN_ALL_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE |		\
-		   IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
-
-static int throttle_cpu;      /* Throttle CPU? */
-static int restart_from_s5;   /* Force system back on from S5 */
-static int fake_pltrst_timeout;  /* Fake PLTRST# timeout at next power-on */
-
-void chipset_force_shutdown(void)
-{
-	CPRINTS("%s()", __func__);
-
-	/*
-	 * Force power off. This condition will reset once the state machine
-	 * transitions to G3.
-	 */
-	gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-}
-
-void chipset_reset(int cold_reset)
-{
-	CPRINTS("%s(%d)", __func__, cold_reset);
-	if (cold_reset) {
-		/*
-		 * Drop and restore PWROK.  This causes the PCH to reboot,
-		 * regardless of its after-G3 setting.  This type of reboot
-		 * causes the PCH to assert PLTRST#, SLP_S3#, and SLP_S5#, so
-		 * we actually drop power to the rest of the system (hence, a
-		 * "cold" reboot).
-		 */
-
-		/* Ignore if PWROK is already low */
-		if (gpio_get_level(GPIO_PCH_SYS_PWROK) == 0)
-			return;
-
-		/* PWROK must deassert for at least 3 RTC clocks = 91 us */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-		udelay(100);
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
-
-	} else {
-		/*
-		 * Send a reset pulse to the PCH.  This just causes it to
-		 * assert INIT# to the CPU without dropping power or asserting
-		 * PLTRST# to reset the rest of the system.  The PCH uses a 16
-		 * ms debounce time, so assert the signal for twice that.
-		 */
-		gpio_set_level(GPIO_PCH_RCIN_L, 0);
-		usleep(32 * MSEC);
-		gpio_set_level(GPIO_PCH_RCIN_L, 1);
-	}
-}
-
-void chipset_throttle_cpu(int throttle)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle);
-}
-
-enum power_state power_chipset_init(void)
-{
-	/* Pause in S5 when shutting down. */
-	power_set_pause_in_s5(1);
-
-	/*
-	 * If we're switching between images without rebooting, see if the x86
-	 * is already powered on; if so, leave it there instead of cycling
-	 * through G3.
-	 */
-	if (system_jumped_to_this_image()) {
-		if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
-			/* Disable idle task deep sleep when in S0. */
-			disable_sleep(SLEEP_MASK_AP_RUN);
-
-			CPRINTS("already in S0");
-			return POWER_S0;
-		} else {
-			/* Force all signals to their G3 states */
-			CPRINTS("forcing G3");
-			gpio_set_level(GPIO_PCH_CORE_PWROK, 0);
-			gpio_set_level(GPIO_VCORE_EN, 0);
-			gpio_set_level(GPIO_SUSP_VR_EN, 0);
-			gpio_set_level(GPIO_PP1350_EN, 0);
-			gpio_set_level(GPIO_PP3300_DX_EN, 0);
-			gpio_set_level(GPIO_PP5000_EN, 0);
-			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-			gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-			wireless_set_state(WIRELESS_OFF);
-		}
-	}
-
-	return POWER_G3;
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_S5:
-		if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 1)
-			return POWER_S5S3; /* Power up to next state */
-		break;
-
-	case POWER_S3:
-		/*
-		 * If lid is closed; hold touchscreen in reset to cut power
-		 * usage.  If lid is open, take touchscreen out of reset so it
-		 * can wake the processor. Chipset task is awakened on lid
-		 * switch transitions.
-		 */
-		gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, lid_is_open());
-
-		/* Check for state transitions */
-		if (!power_has_signals(IN_PGOOD_S3)) {
-			/* Required rail went away */
-			chipset_force_shutdown();
-			return POWER_S3S5;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
-			/* Power up to next state */
-			return POWER_S3S0;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
-		}
-		break;
-
-	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_S0)) {
-			/* Required rail went away */
-			chipset_force_shutdown();
-			return POWER_S0S3;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
-			/* Power down to next state */
-			return POWER_S0S3;
-		}
-		break;
-
-	case POWER_G3S5:
-		/*
-		 * Wait 10ms after +3VALW good, since that powers VccDSW and
-		 * VccSUS.
-		 */
-		msleep(10);
-
-		gpio_set_level(GPIO_SUSP_VR_EN, 1);
-		if (power_wait_signals(IN_PGOOD_S5)) {
-			gpio_set_level(GPIO_SUSP_VR_EN, 0);
-			chipset_force_shutdown();
-			return POWER_G3;
-		}
-
-		/* Deassert RSMRST# */
-		gpio_set_level(GPIO_PCH_RSMRST_L, 1);
-
-		/* Wait 10ms for SUSCLK to stabilize */
-		msleep(10);
-		return POWER_S5;
-
-	case POWER_S5S3:
-		/* Wait for the always-on rails to be good */
-		if (power_wait_signals(IN_PGOOD_ALWAYS_ON)) {
-			chipset_force_shutdown();
-			return POWER_S5G3;
-		}
-
-		/* Turn on power to RAM */
-		gpio_set_level(GPIO_PP1350_EN, 1);
-		if (power_wait_signals(IN_PGOOD_S3)) {
-			chipset_force_shutdown();
-			return POWER_S5G3;
-		}
-
-		/*
-		 * Enable touchpad power so it can wake the system from
-		 * suspend.
-		 */
-		gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-		return POWER_S3;
-
-	case POWER_S3S0:
-		/* Turn on power rails */
-		gpio_set_level(GPIO_PP5000_EN, 1);
-		usleep(3 * MSEC);  /* Small delay; see crosbug.com/p/25271 */
-		gpio_set_level(GPIO_PP3300_DX_EN, 1);
-
-		/* Enable wireless */
-		wireless_set_state(WIRELESS_ON);
-
-		/*
-		 * Make sure touchscreen is out if reset (even if the lid is
-		 * still closed); it may have been turned off if the lid was
-		 * closed in S3.
-		 */
-		gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 1);
-
-		/* Wait for non-core power rails good */
-		if (power_wait_signals(IN_PGOOD_S0)) {
-			chipset_force_shutdown();
-			wireless_set_state(WIRELESS_OFF);
-			gpio_set_level(GPIO_PP3300_DX_EN, 0);
-			gpio_set_level(GPIO_PP5000_EN, 0);
-			gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
-			return POWER_S3;
-		}
-
-		/*
-		 * Enable +CPU_CORE.  The CPU itself will request the supplies
-		 * when it's ready.
-		 */
-		gpio_set_level(GPIO_VCORE_EN, 1);
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Wait 15 ms after all voltages good.  100 ms is only needed
-		 * for PCIe devices; mini-PCIe devices should need only 10 ms.
-		 */
-		msleep(15);
-
-		/*
-		 * Throttle CPU if necessary.  This should only be asserted
-		 * when +VCCP is powered (it is by now).
-		 */
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
-
-		/* Set SYS and CORE PWROK */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
-		gpio_set_level(GPIO_PCH_CORE_PWROK, 1);
-
-		/* Wait 50 ms for platform reset to deassert */
-		{
-			int i;
-
-			for (i = 0; i < 50; i++) {
-				usleep(MSEC);
-				if (!lpc_get_pltrst_asserted())
-					break;
-			}
-
-			if (i < 50 && !fake_pltrst_timeout) {
-				/* Deasserted in time */
-				CPRINTS("power PLTRST# deasserted");
-			} else {
-				/* Force a reset.  See crosbug.com/p/28422 */
-				CPRINTS("power PLTRST# timeout");
-				power_button_pch_release();
-				chipset_force_shutdown();
-				restart_from_s5 = 1;
-
-				fake_pltrst_timeout = 0;
-			}
-		}
-
-		return POWER_S0;
-
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-		/* Clear SYS and CORE PWROK */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-		gpio_set_level(GPIO_PCH_CORE_PWROK, 0);
-
-		/* Wait 40ns */
-		udelay(1);
-
-		/* Disable +CPU_CORE */
-		gpio_set_level(GPIO_VCORE_EN, 0);
-
-		/* Suspend wireless */
-		wireless_set_state(WIRELESS_SUSPEND);
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Deassert prochot since CPU is off and we're about to drop
-		 * +VCCP.
-		 */
-		gpio_set_level(GPIO_CPU_PROCHOT, 0);
-
-		/* Turn off power rails */
-		msleep(7);  /* Small delay; see crosbug.com/p/26561 */
-		gpio_set_level(GPIO_PP3300_DX_EN, 0);
-
-#ifdef CONFIG_USB_PORT_POWER_IN_S3
-		/*
-		 * Disable the 5V rail if all USB ports are disabled.  Else
-		 * leave 5V enabled so the ports will continue to work in S3.
-		 */
-		if (!usb_charge_ports_enabled())
-			gpio_set_level(GPIO_PP5000_EN, 0);
-#else
-		gpio_set_level(GPIO_PP5000_EN, 0);
-#endif
-
-		return POWER_S3;
-
-	case POWER_S3S5:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/* Turn off 5V rail (if it wasn't turned off in S3) */
-		gpio_set_level(GPIO_PP5000_EN, 0);
-
-		/* Disable wireless */
-		wireless_set_state(WIRELESS_OFF);
-
-		/* Disable touchpad power and hold touchscreen in reset */
-		gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
-		gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
-
-		/* Turn off power to RAM */
-		gpio_set_level(GPIO_PP1350_EN, 0);
-
-		/*
-		 * If restarting from S5, delay and fake power button press.
-		 * See crosbug.com/p/28422.
-		 */
-		if (restart_from_s5) {
-			CPRINTS("power restart from S5");
-
-			restart_from_s5 = 0;
-
-			/* Delay for system to shut down after rails dropped */
-			msleep(100);
-
-			/* Restart system via power button press */
-			power_button_pch_pulse();
-
-			/*
-			 * Force system to start back up from scratch.  This is
-			 * needed to undo the effects of a previous call to
-			 * chipset_force_shutdown().
-			 */
-			return POWER_G3S5;
-		}
-
-		/* Start shutting down */
-		return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3;
-
-	case POWER_S5G3:
-		/* Assert RSMRST# */
-		gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-		gpio_set_level(GPIO_SUSP_VR_EN, 0);
-
-		return POWER_G3;
-	}
-
-	return state;
-}
-
-static int console_command_powerfail(int argc, char **argv)
-{
-	ccprintf("Faking a failure of next power-on event\n");
-	fake_pltrst_timeout = 1;
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(powerfail, console_command_powerfail,
-			NULL,
-			"Fake PLTRST# failure during next power-on");
diff --git a/power/build.mk b/power/build.mk
index 6143c3dbbf..21617354cf 100644
--- a/power/build.mk
+++ b/power/build.mk
@@ -7,11 +7,9 @@
 #
 
 power-$(CONFIG_CHIPSET_APOLLOLAKE)+=apollolake.o intel_x86.o
-power-$(CONFIG_CHIPSET_BAYTRAIL)+=baytrail.o
 power-$(CONFIG_CHIPSET_BRASWELL)+=braswell.o
 power-$(CONFIG_CHIPSET_ECDRIVEN)+=ec_driven.o
 power-$(CONFIG_CHIPSET_GAIA)+=gaia.o
-power-$(CONFIG_CHIPSET_HASWELL)+=haswell.o
 power-$(CONFIG_CHIPSET_MEDIATEK)+=mediatek.o
 power-$(CONFIG_CHIPSET_RK3399)+=rk3399.o
 power-$(CONFIG_CHIPSET_ROCKCHIP)+=rockchip.o
diff --git a/power/haswell.c b/power/haswell.c
deleted file mode 100644
index 00a0926f6e..0000000000
--- a/power/haswell.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* X86 haswell chipset power control module for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power.h"
-#include "system.h"
-#include "timer.h"
-#include "util.h"
-#include "wireless.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Input state flags */
-#define IN_PGOOD_PP5000            POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
-#define IN_PGOOD_PP1350            POWER_SIGNAL_MASK(X86_PGOOD_PP1350)
-#define IN_PGOOD_PP1050            POWER_SIGNAL_MASK(X86_PGOOD_PP1050)
-#define IN_PGOOD_VCORE             POWER_SIGNAL_MASK(X86_PGOOD_VCORE)
-#define IN_SLP_S0_DEASSERTED       POWER_SIGNAL_MASK(X86_SLP_S0_DEASSERTED)
-#define IN_SLP_S3_DEASSERTED       POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_SLP_S5_DEASSERTED       POWER_SIGNAL_MASK(X86_SLP_S5_DEASSERTED)
-#define IN_SLP_SUS_DEASSERTED      POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
-
-/* All always-on supplies */
-#define IN_PGOOD_ALWAYS_ON   (IN_PGOOD_PP5000)
-/* All non-core power rails */
-#define IN_PGOOD_ALL_NONCORE (IN_PGOOD_PP1350 | IN_PGOOD_PP1050)
-/* All core power rails */
-#define IN_PGOOD_ALL_CORE    (IN_PGOOD_VCORE)
-/* Rails required for S3 */
-#define IN_PGOOD_S3          (IN_PGOOD_ALWAYS_ON | IN_PGOOD_PP1350)
-/* Rails required for S0 */
-#define IN_PGOOD_S0          (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE)
-
-/* All PM_SLP signals from PCH deasserted */
-#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_DEASSERTED |	\
-				  IN_SLP_S5_DEASSERTED)
-/* All inputs in the right state for S0 */
-#define IN_ALL_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE |		\
-		   IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
-
-static int throttle_cpu;      /* Throttle CPU? */
-
-void chipset_force_shutdown(void)
-{
-	CPRINTS("%s()", __func__);
-
-	/*
-	 * Force power off. This condition will reset once the state machine
-	 * transitions to G3.
-	 */
-	gpio_set_level(GPIO_PCH_DPWROK, 0);
-	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-}
-
-void chipset_reset(int cold_reset)
-{
-	CPRINTS("%s(%d)", __func__, cold_reset);
-	if (cold_reset) {
-		/*
-		 * Drop and restore PWROK.  This causes the PCH to reboot,
-		 * regardless of its after-G3 setting.  This type of reboot
-		 * causes the PCH to assert PLTRST#, SLP_S3#, and SLP_S5#, so
-		 * we actually drop power to the rest of the system (hence, a
-		 * "cold" reboot).
-		 */
-
-		/* Ignore if PWROK is already low */
-		if (gpio_get_level(GPIO_PCH_PWROK) == 0)
-			return;
-
-		/* PWROK must deassert for at least 3 RTC clocks = 91 us */
-		gpio_set_level(GPIO_PCH_PWROK, 0);
-		udelay(100);
-		gpio_set_level(GPIO_PCH_PWROK, 1);
-
-	} else {
-		/*
-		 * Send a RCIN# pulse to the PCH.  This just causes it to
-		 * assert INIT# to the CPU without dropping power or asserting
-		 * PLTRST# to reset the rest of the system.  Pulse must be at
-		 * least 16 PCI clocks long = 500 ns.
-		 */
-
-		/*
-		 * The gpio pin used by the EC (PL6) does not behave in the
-		 * correct manner when configured as open drain. In order to
-		 * mimic open drain, the pin is initially configured as an
-		 * input.  When it is needed to drive low, the flags are
-		 * updated which changes the pin to an output and drives the
-		 * pin low.  Note that this logic will work fine even on boards
-		 * where RCIN# has been moved to a different pin, so there's no
-		 * need to #ifdef this behavior.  See crosbug.com/p/20173.
-		 */
-		gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_OUT_LOW);
-		udelay(10);
-		gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_INPUT);
-	}
-}
-
-void chipset_throttle_cpu(int throttle)
-{
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle);
-}
-
-enum power_state power_chipset_init(void)
-{
-	/* Enable interrupts for our GPIOs */
-	gpio_enable_interrupt(GPIO_PCH_EDP_VDD_EN);
-
-	/*
-	 * If we're switching between images without rebooting, see if the x86
-	 * is already powered on; if so, leave it there instead of cycling
-	 * through G3.
-	 */
-	if (system_jumped_to_this_image()) {
-		if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
-			/* Disable idle task deep sleep when in S0. */
-			disable_sleep(SLEEP_MASK_AP_RUN);
-			CPRINTS("already in S0");
-			return POWER_S0;
-		} else {
-			/* Force all signals to their G3 states */
-			CPRINTS("forcing G3");
-			gpio_set_level(GPIO_PCH_PWROK, 0);
-			gpio_set_level(GPIO_VCORE_EN, 0);
-			gpio_set_level(GPIO_SUSP_VR_EN, 0);
-			gpio_set_level(GPIO_PP1350_EN, 0);
-			gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
-			gpio_set_level(GPIO_PP3300_DX_EN, 0);
-			gpio_set_level(GPIO_PP5000_EN, 0);
-			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-			gpio_set_level(GPIO_PCH_DPWROK, 0);
-			wireless_set_state(WIRELESS_OFF);
-		}
-	}
-
-	return POWER_G3;
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_S5:
-		if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 1)
-			return POWER_S5S3; /* Power up to next state */
-		break;
-
-	case POWER_S3:
-		/*
-		 * If lid is closed; hold touchscreen in reset to cut power
-		 * usage.  If lid is open, take touchscreen out of reset so it
-		 * can wake the processor. Chipset task is awakened on lid
-		 * switch transitions.
-		 */
-		gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, lid_is_open());
-
-		/* Check for state transitions */
-		if (!power_has_signals(IN_PGOOD_S3)) {
-			/* Required rail went away */
-			chipset_force_shutdown();
-			return POWER_S3S5;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
-			/* Power up to next state */
-			return POWER_S3S0;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
-		}
-		break;
-
-	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_S0)) {
-			/* Required rail went away */
-			chipset_force_shutdown();
-			return POWER_S0S3;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
-			/* Power down to next state */
-			return POWER_S0S3;
-		}
-		break;
-
-	case POWER_G3S5:
-		/*
-		 * Wait 10ms after +3VALW good, since that powers VccDSW and
-		 * VccSUS.
-		 */
-		msleep(10);
-
-		/* Assert DPWROK */
-		gpio_set_level(GPIO_PCH_DPWROK, 1);
-		if (power_wait_signals(IN_SLP_SUS_DEASSERTED)) {
-			chipset_force_shutdown();
-			return POWER_G3;
-		}
-
-		gpio_set_level(GPIO_SUSP_VR_EN, 1);
-		if (power_wait_signals(IN_PGOOD_PP1050)) {
-			gpio_set_level(GPIO_SUSP_VR_EN, 0);
-			chipset_force_shutdown();
-			return POWER_G3;
-		}
-
-		/* Deassert RSMRST# */
-		gpio_set_level(GPIO_PCH_RSMRST_L, 1);
-
-		/* Wait 5ms for SUSCLK to stabilize */
-		msleep(5);
-		return POWER_S5;
-
-	case POWER_S5S3:
-		/* Enable PP5000 (5V) rail. */
-		gpio_set_level(GPIO_PP5000_EN, 1);
-		if (power_wait_signals(IN_PGOOD_PP5000)) {
-			chipset_force_shutdown();
-			return POWER_S5G3;
-		}
-
-		/* Wait for the always-on rails to be good */
-		if (power_wait_signals(IN_PGOOD_ALWAYS_ON)) {
-			chipset_force_shutdown();
-			return POWER_S5G3;
-		}
-
-		/* Turn on power to RAM */
-		gpio_set_level(GPIO_PP1350_EN, 1);
-		if (power_wait_signals(IN_PGOOD_S3)) {
-			chipset_force_shutdown();
-			return POWER_S5G3;
-		}
-
-		/*
-		 * Enable touchpad power so it can wake the system from
-		 * suspend.
-		 */
-		gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-		return POWER_S3;
-
-	case POWER_S3S0:
-		/* Turn on power rails */
-		gpio_set_level(GPIO_PP3300_DX_EN, 1);
-
-		/* Enable wireless */
-		wireless_set_state(WIRELESS_ON);
-
-		/*
-		 * Make sure touchscreen is out if reset (even if the lid is
-		 * still closed); it may have been turned off if the lid was
-		 * closed in S3.
-		 */
-		gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 1);
-
-		/* Wait for non-core power rails good */
-		if (power_wait_signals(IN_PGOOD_S0)) {
-			chipset_force_shutdown();
-			wireless_set_state(WIRELESS_OFF);
-			gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
-			gpio_set_level(GPIO_PP3300_DX_EN, 0);
-			gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
-			return POWER_S3;
-		}
-
-		/*
-		 * Enable +CPU_CORE.  The CPU itself will request the supplies
-		 * when it's ready.
-		 */
-		gpio_set_level(GPIO_VCORE_EN, 1);
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/* Wait 99ms after all voltages good */
-		msleep(99);
-
-		/*
-		 * Throttle CPU if necessary.  This should only be asserted
-		 * when +VCCP is powered (it is by now).
-		 */
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
-
-		/* Set PCH_PWROK */
-		gpio_set_level(GPIO_PCH_PWROK, 1);
-		gpio_set_level(GPIO_SYS_PWROK, 1);
-		return POWER_S0;
-
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-		/* Clear PCH_PWROK */
-		gpio_set_level(GPIO_SYS_PWROK, 0);
-		gpio_set_level(GPIO_PCH_PWROK, 0);
-
-		/* Wait 40ns */
-		udelay(1);
-
-		/* Disable +CPU_CORE */
-		gpio_set_level(GPIO_VCORE_EN, 0);
-
-		/* Suspend wireless */
-		wireless_set_state(WIRELESS_SUSPEND);
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Deassert prochot since CPU is off and we're about to drop
-		 * +VCCP.
-		 */
-		gpio_set_level(GPIO_CPU_PROCHOT, 0);
-
-		/* Turn off power rails */
-		gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
-		gpio_set_level(GPIO_PP3300_DX_EN, 0);
-		return POWER_S3;
-
-	case POWER_S3S5:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/* Disable wireless */
-		wireless_set_state(WIRELESS_OFF);
-
-		/* Disable touchpad power */
-		gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
-
-		/* Turn off power to RAM */
-		gpio_set_level(GPIO_PP1350_EN, 0);
-
-		/* Disable PP5000 (5V) rail. */
-		gpio_set_level(GPIO_PP5000_EN, 0);
-
-		/* Start shutting down */
-		return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3;
-
-	case POWER_S5G3:
-		/* Deassert DPWROK, assert RSMRST# */
-		gpio_set_level(GPIO_PCH_DPWROK, 0);
-		gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-		gpio_set_level(GPIO_SUSP_VR_EN, 0);
-		return POWER_G3;
-	}
-
-	return state;
-}
-
-void power_interrupt(enum gpio_signal signal)
-{
-	/* Pass through eDP VDD enable from PCH */
-	gpio_set_level(GPIO_EC_EDP_VDD_EN, gpio_get_level(GPIO_PCH_EDP_VDD_EN));
-}