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author | Kevin K Wong <kevin.k.wong@intel.com> | 2016-04-14 11:28:40 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2016-04-15 12:12:58 -0700 |
commit | fef9abf3b3473dad728e2f2bd8557e230214f03d (patch) | |
tree | ce259adc6e681c89b0de479421ca5494b0de9ca4 /power | |
parent | b72c096f20a0520ff794cc871073677bdb0cdec7 (diff) | |
download | chrome-ec-fef9abf3b3473dad728e2f2bd8557e230214f03d.tar.gz |
apollolake: Remove timing delay for SOC_PWROK and RSMRST_N
PMIC already has a built-in 100ms delay for V1P05S when ALL_SYS_PWRGD
asserts, hence EC can assert SOC_PWROK immediately. On shutdown RSMRST_N
should assert and SOC_PWR_OK should de-assert immediately when PMIC asserts
PMIC_RSMRST_N and de-assert All_SYS_PWRGD respectively. Hence removed
the unnecessary timing delay for SOC_PWROK and RSMRST_N.
BUG=none
BRANCH=none
TEST=Issued a shutdown command and manually tested on amenia.
RSMRST_N asserts immediately when PMIC asserts PMIC_RSMRST_N
SOC_PWR_OK de-asserts immediately when PMIC de-asserts All_SYS_PWRGD.
Change-Id: I8bb79277a3dcf8545764ba58736f422ac377776e
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/339001
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'power')
-rw-r--r-- | power/apollolake.c | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/power/apollolake.c b/power/apollolake.c index a4f7bf27e4..df486ff394 100644 --- a/power/apollolake.c +++ b/power/apollolake.c @@ -113,8 +113,7 @@ enum power_state power_chipset_init(void) static void handle_pass_through(enum power_state state, enum gpio_signal pin_in, - enum gpio_signal pin_out, - int pass_through_delay) + enum gpio_signal pin_out) { /* * Pass through asynchronously, as SOC may not react @@ -126,12 +125,6 @@ static void handle_pass_through(enum power_state state, /* Nothing to do. */ if (in_level == out_level) return; - /* - * Wait at least 10ms between power signals going high - * and pass through to SOC. - */ - if (in_level) - msleep(MAX(10, pass_through_delay)); gpio_set_level(pin_out, in_level); @@ -396,10 +389,10 @@ enum power_state power_handle_state(enum power_state state) enum power_state new_state; /* Process RSMRST_L state changes. */ - handle_pass_through(state, GPIO_RSMRST_L_PGOOD, GPIO_PCH_RSMRST_L, 0); + handle_pass_through(state, GPIO_RSMRST_L_PGOOD, GPIO_PCH_RSMRST_L); /* Process ALL_SYS_PGOOD state changes. */ - handle_pass_through(state, GPIO_ALL_SYS_PGOOD, GPIO_PCH_SYS_PWROK, 0); + handle_pass_through(state, GPIO_ALL_SYS_PGOOD, GPIO_PCH_SYS_PWROK); new_state = _power_handle_state(state); |