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| author | Aseda Aboagye <aaboagye@google.com> | 2017-12-20 11:29:51 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-12-20 18:32:01 -0800 |
| commit | 4a7aceed59e1ff3df7078859aac4031befd64b11 (patch) | |
| tree | 469f792f9d1d0e403c9960af458c0f8a3c2d9fd3 /power | |
| parent | 7c688c0f698ec969ac53dda851b96c3e3cce55b2 (diff) | |
| download | chrome-ec-4a7aceed59e1ff3df7078859aac4031befd64b11.tar.gz | |
power: cannonlake: SLP_SUS_L deasserted == S5.
When SLP_SUS_L is deasserted, that means the chipset is in S5.
BUG=None
BRANCH=None
TEST=Flash meowth; boot from AC only, verify that when SoC actually
boots the power state is reported as S0 instead of G3.
Change-Id: Ib9cd76aa9efd6f81df432205b8c1e8c342e32af6
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/837485
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/cannonlake.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/power/cannonlake.c b/power/cannonlake.c index b07114eced..7a1241363f 100644 --- a/power/cannonlake.c +++ b/power/cannonlake.c @@ -113,6 +113,12 @@ enum power_state power_handle_state(enum power_state state) } switch (state) { + case POWER_G3: + /* If SLP_SUS_L is deasserted, we're no longer in G3. */ + if (power_has_signals(IN_PCH_SLP_SUS_DEASSERTED)) + return POWER_S5; + break; + case POWER_G3S5: /* Turn on the PP3300_DSW rail. */ gpio_set_level(GPIO_EN_PP3300_DSW, 1); |