intel_x86: Handle RSMRST signal in Intel x86 common code

BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
     Reef can boot to OS. S3, S5, hibernate are working.

Change-Id: Iddd16cba5f1dc62341dfbc8568b490439b7d593b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/427018
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 58 insertions, 73 deletions

diff --git a/power/apollolake.c b/power/apollolake.c
index 43e4360ba2..c3ca7f55f5 100644
--- a/power/apollolake.c
+++ b/power/apollolake.c
@@ -63,28 +63,6 @@ void chipset_reset(int cold_reset)
 	}
 }
 
-void handle_rsmrst(enum power_state state)
-{
-	/*
-	 * Pass through asynchronously, as SOC may not react
-	 * immediately to power changes.
-	 */
-	int in_level = gpio_get_level(GPIO_RSMRST_L_PGOOD);
-	int out_level = gpio_get_level(GPIO_PCH_RSMRST_L);
-
-	/* Nothing to do. */
-	if (in_level == out_level)
-		return;
-
-	/* Only passthrough RSMRST_L de-assertion on power up */
-	if (in_level && !power_s5_up)
-		return;
-
-	gpio_set_level(GPIO_PCH_RSMRST_L, in_level);
-
-	CPRINTS("Pass through GPIO_RSMRST_L_PGOOD: %d", in_level);
-}
-
 static void handle_all_sys_pgood(enum power_state state)
 {
 	/*
@@ -132,7 +110,7 @@ rsmrst_handle:
 	 * RSMRST_L is also checked in some states and, if asserted, will
 	 * force shutdown.
 	 */
-	handle_rsmrst(new_state);
+	common_intel_x86_handle_rsmrst(new_state);
 
 	return new_state;
 }
diff --git a/power/intel_x86.c b/power/intel_x86.c
index ed43017f6b..3fe3e68736 100644
--- a/power/intel_x86.c
+++ b/power/intel_x86.c
@@ -5,6 +5,7 @@
 
 /* Intel X86 chipset power control module for Chrome EC */
 
+#include "board_config.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "console.h"
@@ -32,31 +33,32 @@
 #define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
 
 enum sys_sleep_state {
-	SYS_SLEEP_S5,
-	SYS_SLEEP_S4,
-	SYS_SLEEP_S3
+	SYS_SLEEP_S3,
+	SYS_SLEEP_S4
 };
 
-int power_s5_up;       /* Chipset is sequencing up or down */
+#ifdef CONFIG_ESPI_VW_SIGNALS
+static const enum espi_vw_signal espi_vm_sig[] = {
+	[SYS_SLEEP_S3] = VW_SLP_S3_L,
+	[SYS_SLEEP_S4] = VW_SLP_S4_L,
+};
+#else
+static const enum gpio_signal gpio_sig[] = {
+	[SYS_SLEEP_S3] = GPIO_PCH_SLP_S3_L,
+	[SYS_SLEEP_S4] = GPIO_PCH_SLP_S4_L,
+};
+#endif
+
+static int power_s5_up;       /* Chipset is sequencing up or down */
 
 /* Get system sleep state through GPIOs or VWs */
-static int chipset_get_sleep_signal(enum sys_sleep_state state)
+static inline int chipset_get_sleep_signal(enum sys_sleep_state state)
 {
 #ifdef CONFIG_ESPI_VW_SIGNALS
-	if (state == SYS_SLEEP_S4)
-		return espi_vw_get_wire(VW_SLP_S4_L);
-	else if (state == SYS_SLEEP_S3)
-		return espi_vw_get_wire(VW_SLP_S3_L);
+	return espi_vw_get_wire(espi_vm_sig[state]);
 #else
-	if (state == SYS_SLEEP_S4)
-		return gpio_get_level(GPIO_PCH_SLP_S4_L);
-	else if (state == SYS_SLEEP_S3)
-		return gpio_get_level(GPIO_PCH_SLP_S3_L);
+	return gpio_get_level(gpio_sig[state]);
 #endif
-
-	/* We should never run here */
-	ASSERT(0);
-	return 0;
 }
 
 #ifdef CONFIG_BOARD_HAS_RTC_RESET
@@ -67,7 +69,7 @@ static enum power_state power_wait_s5_rtc_reset(void)
 	/* Wait for S5 exit and then attempt RTC reset */
 	while ((power_get_signals() & IN_PCH_SLP_S4_DEASSERTED) == 0) {
 		/* Handle RSMRST passthru event while waiting */
-		handle_rsmrst(POWER_S5);
+		common_intel_x86_handle_rsmrst(POWER_S5);
 		if (task_wait_event(SECOND*4) == TASK_EVENT_TIMER) {
 			CPRINTS("timeout waiting for S5 exit");
 			chipset_force_g3();
@@ -380,3 +382,38 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 
 	return state;
 }
+
+void common_intel_x86_handle_rsmrst(enum power_state state)
+{
+	/*
+	 * Pass through RSMRST asynchronously, as PCH may not react
+	 * immediately to power changes.
+	 */
+	int rsmrst_in = gpio_get_level(GPIO_RSMRST_L_PGOOD);
+	int rsmrst_out = gpio_get_level(GPIO_PCH_RSMRST_L);
+
+	/* Nothing to do. */
+	if (rsmrst_in == rsmrst_out)
+		return;
+
+#ifdef CONFIG_BOARD_HAS_BEFORE_RSMRST
+	board_before_rsmrst(rsmrst_in);
+#endif
+
+#ifdef CONFIG_CHIPSET_APOLLOLAKE
+	/* Only passthrough RSMRST_L de-assertion on power up */
+	if (rsmrst_in && !power_s5_up)
+		return;
+#elif defined(CONFIG_CHIPSET_SKYLAKE)
+	/*
+	 * Wait at least 10ms between power signals going high
+	 * and deasserting RSMRST to PCH.
+	 */
+	if (rsmrst_in)
+		msleep(10);
+#endif
+
+	gpio_set_level(GPIO_PCH_RSMRST_L, rsmrst_in);
+
+	CPRINTS("Pass through GPIO_RSMRST_L_PGOOD: %d", rsmrst_in);
+}
diff --git a/power/intel_x86.h b/power/intel_x86.h
index 614f0197b1..70a1a66e65 100644
--- a/power/intel_x86.h
+++ b/power/intel_x86.h
@@ -11,14 +11,12 @@
 
 #include "power.h"
 
-extern int power_s5_up;       /* Chipset is sequencing up or down */
-
 /**
  * Handle RSMRST signal.
  *
  * @param state Current chipset state.
  */
-void handle_rsmrst(enum power_state state);
+void common_intel_x86_handle_rsmrst(enum power_state state);
 
 /**
  * Force chipset to G3 state.
diff --git a/power/skylake.c b/power/skylake.c
index c821ecb268..2e5425a794 100644
--- a/power/skylake.c
+++ b/power/skylake.c
@@ -5,7 +5,6 @@
 
 /* Skylake IMVP8 / ROP PMIC chipset power control module for Chrome EC */
 
-#include "board_config.h"
 #include "chipset.h"
 #include "console.h"
 #include "gpio.h"
@@ -81,33 +80,6 @@ void chipset_reset(int cold_reset)
 	}
 }
 
-void handle_rsmrst(enum power_state state)
-{
-	/*
-	 * Pass through RSMRST asynchronously, as PCH may not react
-	 * immediately to power changes.
-	 */
-	int rsmrst_in = gpio_get_level(GPIO_RSMRST_L_PGOOD);
-	int rsmrst_out = gpio_get_level(GPIO_PCH_RSMRST_L);
-
-	/* Nothing to do. */
-	if (rsmrst_in == rsmrst_out)
-		return;
-
-#ifdef CONFIG_BOARD_HAS_BEFORE_RSMRST
-	board_before_rsmrst(rsmrst_in);
-#endif
-
-	/*
-	 * Wait at least 10ms between power signals going high
-	 * and deasserting RSMRST to PCH.
-	 */
-	if (rsmrst_in)
-		msleep(10);
-	gpio_set_level(GPIO_PCH_RSMRST_L, rsmrst_in);
-	CPRINTS("RSMRST: %d", rsmrst_in);
-}
-
 static void handle_slp_sus(enum power_state state)
 {
 	/* If we're down or going down don't do anythin with SLP_SUS_L. */
@@ -123,7 +95,7 @@ enum power_state power_handle_state(enum power_state state)
 	enum power_state new_state;
 
 	/* Process RSMRST_L state changes. */
-	handle_rsmrst(state);
+	common_intel_x86_handle_rsmrst(state);
 
 	if (state == POWER_S5 && forcing_shutdown) {
 		power_button_pch_release();