summaryrefslogtreecommitdiff
path: root/power
diff options
context:
space:
mode:
authorFurquan Shaikh <furquan@chromium.org>2017-07-17 23:41:07 -0700
committerchrome-bot <chrome-bot@chromium.org>2017-07-18 21:50:33 -0700
commitef73893a4b73e9181382530dd98dd28b1de52c38 (patch)
tree773f218573cfc32bb03c7a75878cb2464d1cf866 /power
parent592805e75fc742709c7db82020f3b3e38b30f314 (diff)
downloadchrome-ec-ef73893a4b73e9181382530dd98dd28b1de52c38.tar.gz
skylake: Use SYS_RESET signal to trigger warm and cold reset
RCIN# signal is known to not work properly for performing a warm reset when the CPU is in a bad state. This results in the common key combo (Alt-Volup-r) not working to reset the host. Thus, use SYS_RESET signal instead to trigger both cold and warm chipset reset. BUG=chromium:721853 BRANCH=None TEST=make -j buildall Change-Id: I38663db96767d0aa03cd1aea0fe2a0cc5b771cd2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/575947 Reviewed-by: Duncan Laurie <dlaurie@google.com>
Diffstat (limited to 'power')
-rw-r--r--power/skylake.c35
1 files changed, 12 insertions, 23 deletions
diff --git a/power/skylake.c b/power/skylake.c
index 8f9533d79a..e2a072c9df 100644
--- a/power/skylake.c
+++ b/power/skylake.c
@@ -58,29 +58,18 @@ void chipset_reset(int cold_reset)
{
CPRINTS("%s(%d)", __func__, cold_reset);
- if (cold_reset) {
- if (gpio_get_level(GPIO_SYS_RESET_L) == 0)
- return;
- gpio_set_level(GPIO_SYS_RESET_L, 0);
- /* Debounce time for SYS_RESET_L is 16 ms */
- udelay(20 * MSEC);
- gpio_set_level(GPIO_SYS_RESET_L, 1);
- } else {
- /*
- * Send a RCIN_PCH_RCIN_L
- * assert INIT# to the CPU without dropping power or asserting
- * PLTRST# to reset the rest of the system.
- */
-
- /* Pulse must be at least 16 PCI clocks long = 500 ns */
-#ifdef CONFIG_ESPI_VW_SIGNALS
- lpc_host_reset();
-#else
- gpio_set_level(GPIO_PCH_RCIN_L, 0);
- udelay(10);
- gpio_set_level(GPIO_PCH_RCIN_L, 1);
-#endif
- }
+ /*
+ * Irrespective of cold_reset value, always toggle SYS_RESET_L to
+ * perform a chipset reset. RCIN# which was used earlier to trigger a
+ * warm reset is known to not work in certain cases where the CPU is in
+ * a bad state (crbug.com/721853)
+ */
+ if (gpio_get_level(GPIO_SYS_RESET_L) == 0)
+ return;
+ gpio_set_level(GPIO_SYS_RESET_L, 0);
+ /* Debounce time for SYS_RESET_L is 16 ms */
+ udelay(20 * MSEC);
+ gpio_set_level(GPIO_SYS_RESET_L, 1);
}
static void handle_slp_sus(enum power_state state)