diff options
author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2018-03-21 13:54:59 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-25 00:50:40 -0700 |
commit | 3e12d9af2077ce33e773ef538cc0ee975d2d14d7 (patch) | |
tree | 08a8cf02c53cbd72fe87ad6cf35382f95869ba96 /power | |
parent | e94bf79f85a74f6c6bd6f4b4bc258abf2ea7e586 (diff) | |
download | chrome-ec-3e12d9af2077ce33e773ef538cc0ee975d2d14d7.tar.gz |
intel_x86: Move chipset reset logic to common code
Chipset reset logic chipset_reset() is same for APL, GLK,
SKL, KBL and CNL hence move it to common code.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Change-Id: I289e9807d53e397e62d650289e80b6ce25fe399e
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974471
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'power')
-rw-r--r-- | power/apollolake.c | 12 | ||||
-rw-r--r-- | power/cannonlake.c | 20 | ||||
-rw-r--r-- | power/intel_x86.c | 31 | ||||
-rw-r--r-- | power/skylake.c | 18 |
4 files changed, 31 insertions, 50 deletions
diff --git a/power/apollolake.c b/power/apollolake.c index 5e3aa3d33f..69d253c8fd 100644 --- a/power/apollolake.c +++ b/power/apollolake.c @@ -37,18 +37,6 @@ void chipset_handle_espi_reset_assert(void) { } -void chipset_reset(int cold_reset) -{ - CPRINTS("%s", __func__); - - /* - * Send a pulse to SOC PMU_RSTBTN_N to trigger a warm reset. - */ - gpio_set_level(GPIO_SYS_RESET_L, 0); - usleep(32 * MSEC); - gpio_set_level(GPIO_SYS_RESET_L, 1); -} - static void handle_all_sys_pgood(enum power_state state) { /* diff --git a/power/cannonlake.c b/power/cannonlake.c index 7a1241363f..47b1c912f0 100644 --- a/power/cannonlake.c +++ b/power/cannonlake.c @@ -52,26 +52,6 @@ void chipset_handle_espi_reset_assert(void) } } -void chipset_reset(int cold_reset) -{ - /* - * The EC cannot control warm vs cold reset of the chipset using - * SYS_RESET_L; it's more of a request. - */ - CPRINTS("%s()", __func__); - - if (gpio_get_level(GPIO_SYS_RESET_L) == 0) - return; - - /* - * Debounce time for SYS_RESET_L is 16 ms. Wait twice that period to be - * safe. - */ - gpio_set_level(GPIO_SYS_RESET_L, 0); - udelay(32 * MSEC); - gpio_set_level(GPIO_SYS_RESET_L, 1); -} - enum power_state chipset_force_g3(void) { int timeout = 50; diff --git a/power/intel_x86.c b/power/intel_x86.c index 2e983c514c..73cac45613 100644 --- a/power/intel_x86.c +++ b/power/intel_x86.c @@ -509,3 +509,34 @@ void power_chipset_handle_host_sleep_event(enum host_sleep_event state) } #endif + +void chipset_reset(int cold_reset) +{ + /* + * Irrespective of cold_reset value, always toggle SYS_RESET_L to + * perform a chipset reset. RCIN# which was used earlier to trigger + * a warm reset is known to not work in certain cases where the CPU + * is in a bad state (crbug.com/721853). + * + * The EC cannot control warm vs cold reset of the chipset using + * SYS_RESET_L; it's more of a request. + */ + CPRINTS("%s", __func__); + + /* + * Toggling SYS_RESET_L will not have any impact when it's already + * low (i,e. Chipset is in reset state). + */ + if (gpio_get_level(GPIO_SYS_RESET_L) == 0) { + CPRINTS("Chipset is in reset state"); + return; + } + + gpio_set_level(GPIO_SYS_RESET_L, 0); + /* + * Debounce time for SYS_RESET_L is 16 ms. Wait twice that period + * to be safe. + */ + udelay(32 * MSEC); + gpio_set_level(GPIO_SYS_RESET_L, 1); +} diff --git a/power/skylake.c b/power/skylake.c index 61c07fb70e..8df01c542f 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -54,24 +54,6 @@ enum power_state chipset_force_g3(void) return POWER_G3; } -void chipset_reset(int cold_reset) -{ - CPRINTS("%s(%d)", __func__, cold_reset); - - /* - * Irrespective of cold_reset value, always toggle SYS_RESET_L to - * perform a chipset reset. RCIN# which was used earlier to trigger a - * warm reset is known to not work in certain cases where the CPU is in - * a bad state (crbug.com/721853) - */ - if (gpio_get_level(GPIO_SYS_RESET_L) == 0) - return; - gpio_set_level(GPIO_SYS_RESET_L, 0); - /* Debounce time for SYS_RESET_L is 16 ms */ - udelay(20 * MSEC); - gpio_set_level(GPIO_SYS_RESET_L, 1); -} - static void handle_slp_sus(enum power_state state) { /* If we're down or going down don't do anythin with SLP_SUS_L. */ |