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| author | Nicolas Boichat <drinkcat@chromium.org> | 2018-10-15 14:30:11 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-10-15 08:46:25 -0700 |
| commit | e64f68f402450419a70478a734d3e383f5c9416d (patch) | |
| tree | cb4380bce9931ac46604ea3801127b6dca749d3b /power | |
| parent | c0847323192309878855a8e9e85fda91afac5c0d (diff) | |
| download | chrome-ec-e64f68f402450419a70478a734d3e383f5c9416d.tar.gz | |
power/mt8183: Reboot EC before trying to boot AP for a second time
HW will prevent us from asserting AP_SYS_RST_L a second time,
so we need to reset the EC.
BRANCH=none
BUG=b:117244116
TEST=Boot kukui => apshutdown => powerb, see that EC resets itself
Change-Id: I55236db05777652c171a71dc3fd15fafd7d87434
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1278223
Reviewed-by: Yilun Lin <yllin@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/mt8183.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/power/mt8183.c b/power/mt8183.c index a268181c1e..1aea2535cf 100644 --- a/power/mt8183.c +++ b/power/mt8183.c @@ -168,6 +168,12 @@ static void power_seq_run(const struct power_seq_op *power_seq_ops, enum power_state power_handle_state(enum power_state state) { + /* + * Set if we already had a rising edge on AP_SYS_RST_L. If so, any + * subsequent boot attempt will require an EC reset. + */ + static int booted; + /* Retry S5->S3 transition, if not zero. */ static int s5s3_retry; @@ -218,8 +224,8 @@ enum power_state power_handle_state(enum power_state state) gpio_set_level(GPIO_PMIC_EN_ODL, 1); } - /* If EC is in RW, reboot to RO. */ - if (system_get_image_copy() != SYSTEM_IMAGE_RO) { + /* If EC is in RW, or has already booted once, reboot to RO. */ + if (system_get_image_copy() != SYSTEM_IMAGE_RO || booted) { /* * TODO(b:109850749): How quickly does the EC come back * up? Would IN_PGOOD_PMIC be ready by the time we are @@ -227,7 +233,7 @@ enum power_state power_handle_state(enum power_state state) * after debounce (32 ms), minus PMIC_EN_PULSE_MS above. * It would be good to avoid another _EN pulse above. */ - chipset_reset(CHIPSET_RESET_INIT); + chipset_reset(CHIPSET_RESET_AP_REQ); } /* @@ -245,6 +251,7 @@ enum power_state power_handle_state(enum power_state state) return POWER_S5G3; } + booted = 1; /* Enable S3 power supplies, release AP reset. */ power_seq_run(s5s3_power_seq, ARRAY_SIZE(s5s3_power_seq)); |