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| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2019-09-04 15:59:45 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-09-05 23:04:33 +0000 |
| commit | df7ecbc55f4b7d67174a14db9dc781789f07ac60 (patch) | |
| tree | 1a96ae424a2a2400fc81b9d0b313f8ef435aa0e0 /power | |
| parent | b47a5ca84dfd6b75a4cd76837d81cac0345c000f (diff) | |
| download | chrome-ec-df7ecbc55f4b7d67174a14db9dc781789f07ac60.tar.gz | |
power: Add power sequencing logic for Tigerlake chipset
Power sequencing logic for Tigerlake is same as Icelake hence
reusing the Icelake code.
BUG=b:140508849
BRANCH=none
TEST=tglrvp can boot to S0
Change-Id: Id218422146e5549aa5b246ddbcaedd8e442e376b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1785685
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/build.mk | 2 | ||||
| -rw-r--r-- | power/intel_x86.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/power/build.mk b/power/build.mk index 3b001e3596..8a75b86b6b 100644 --- a/power/build.mk +++ b/power/build.mk @@ -11,7 +11,7 @@ power-$(CONFIG_CHIPSET_BRASWELL)+=braswell.o power-$(CONFIG_CHIPSET_CANNONLAKE)+=cannonlake.o intel_x86.o power-$(CONFIG_CHIPSET_COMETLAKE)+=cometlake.o intel_x86.o power-$(CONFIG_CHIPSET_ECDRIVEN)+=ec_driven.o -power-$(CONFIG_CHIPSET_ICELAKE)+=icelake.o intel_x86.o +power-$(CONFIG_CHIPSET_ICL_TGL)+=icelake.o intel_x86.o power-$(CONFIG_CHIPSET_MT817X)+=mt817x.o power-$(CONFIG_CHIPSET_MT8183)+=mt8183.o power-$(CONFIG_CHIPSET_RK3288)+=rk3288.o diff --git a/power/intel_x86.h b/power/intel_x86.h index 452b033838..f6f5f311b8 100644 --- a/power/intel_x86.h +++ b/power/intel_x86.h @@ -20,7 +20,7 @@ #include "cannonlake.h" #elif defined(CONFIG_CHIPSET_COMETLAKE) #include "cometlake.h" -#elif defined(CONFIG_CHIPSET_ICELAKE) +#elif defined(CONFIG_CHIPSET_ICL_TGL) #include "icelake.h" #elif defined(CONFIG_CHIPSET_SKYLAKE) #include "skylake.h" |