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| author | Rob Barnes <robbarnes@google.com> | 2021-03-16 12:49:29 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-16 22:14:08 +0000 |
| commit | d6d9d8df94eb427a64d46c04dde659cc8d378dff (patch) | |
| tree | 472c27c4e40d9709c7b46a9c3952c16b9ee37b78 /power | |
| parent | b902ab52f0926406ebaf0b6f80c3ecfb465b9909 (diff) | |
| download | chrome-ec-d6d9d8df94eb427a64d46c04dde659cc8d378dff.tar.gz | |
guybrush: Enable CONFIG_CHIPSET_X86_RSMRST_DELAY
Add a delay of 10ms between S5_PGOOD and RSMRST_L. Needed to meet timing
specs. 10ms matches what is used on Intel. This may need to be tuned for
AMD chipsets.
BUG=b:182802230
TEST=Build
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I8e2c5a2b47866496a1ae598089e4ac5aa5fa45d3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2764971
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/amd_x86.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/power/amd_x86.c b/power/amd_x86.c index e7e706c4cc..ab62f7b06e 100644 --- a/power/amd_x86.c +++ b/power/amd_x86.c @@ -157,6 +157,10 @@ static void handle_pass_through(enum gpio_signal pin_in, if ((pin_in == GPIO_S0_PGOOD) && in_level) msleep(1); + if (IS_ENABLED(CONFIG_CHIPSET_X86_RSMRST_DELAY) && + (pin_out == GPIO_PCH_RSMRST_L) && in_level) + msleep(10); + gpio_set_level(pin_out, in_level); CPRINTS("Pass through %s: %d", gpio_get_name(pin_in), in_level); |