summaryrefslogtreecommitdiff
path: root/power
diff options
context:
space:
mode:
authorScott Collyer <scollyer@google.com>2018-12-13 15:52:01 -0800
committerchrome-bot <chrome-bot@chromium.org>2019-01-24 00:51:29 -0800
commit1e412f17f0d9753bc7b135967016f6e2c66c7f1f (patch)
tree7ed58fdfbe74896e738b58c9ecfd486406cd48e8 /power
parentea9913e368cabf00666a691eecb0fa61badd9da2 (diff)
downloadchrome-ec-1e412f17f0d9753bc7b135967016f6e2c66c7f1f.tar.gz
cometlake: Add power sequencing support for cometlake chipset
This CL adds cometlake specific portions of power sequencing. BRANCH=none BUG=b:122251649 TEST=make buildall, verified in factory that AP gets to S0 Change-Id: I84726cd522ab55ca9ec095b94392ffa387fb253f Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1377570 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'power')
-rw-r--r--power/build.mk1
-rw-r--r--power/cometlake.c137
-rw-r--r--power/cometlake.h28
-rw-r--r--power/intel_x86.c2
4 files changed, 168 insertions, 0 deletions
diff --git a/power/build.mk b/power/build.mk
index 69eece1c36..1e8cc416e6 100644
--- a/power/build.mk
+++ b/power/build.mk
@@ -9,6 +9,7 @@
power-$(CONFIG_CHIPSET_APL_GLK)+=apollolake.o intel_x86.o
power-$(CONFIG_CHIPSET_BRASWELL)+=braswell.o
power-$(CONFIG_CHIPSET_CANNONLAKE)+=cannonlake.o intel_x86.o
+power-$(CONFIG_CHIPSET_COMETLAKE)+=cometlake.o intel_x86.o
power-$(CONFIG_CHIPSET_ECDRIVEN)+=ec_driven.o
power-$(CONFIG_CHIPSET_ICELAKE)+=icelake.o intel_x86.o
power-$(CONFIG_CHIPSET_MT817X)+=mt817x.o
diff --git a/power/cometlake.c b/power/cometlake.c
new file mode 100644
index 0000000000..27b78efa32
--- /dev/null
+++ b/power/cometlake.c
@@ -0,0 +1,137 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Cometlake chipset power control module for Chrome EC */
+
+#include "cometlake.h"
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "intel_x86.h"
+#include "power.h"
+#include "power_button.h"
+#include "task.h"
+#include "timer.h"
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+
+static int forcing_shutdown; /* Forced shutdown in progress? */
+
+void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+{
+ int timeout_ms = 50;
+
+ CPRINTS("%s(%d)", __func__, reason);
+ report_ap_reset(reason);
+
+ /* Turn off A (except PP5000_A) rails*/
+ gpio_set_level(GPIO_EN_A_RAILS, 0);
+
+ /* Turn off PP5000_A rail */
+ gpio_set_level(GPIO_EN_PP5000_A, 0);
+
+ /* Need to wait a min of 10 msec before check for power good */
+ msleep(10);
+
+ /*
+ * TODO(b/122264541): Replace this wait with
+ * power_wait_signals_timeout()
+ */
+ /* Now wait for PP5000_A and RSMRST_L to go low */
+ while ((gpio_get_level(GPIO_PP5000_A_PG_OD) ||
+ power_has_signals(IN_PGOOD_ALL_CORE)) && (timeout_ms > 0)) {
+ msleep(1);
+ timeout_ms--;
+ };
+
+ if (!timeout_ms)
+ CPRINTS("PP5000_A rail still up! Assuming G3.");
+}
+
+void chipset_handle_espi_reset_assert(void)
+{
+ /*
+ * If eSPI_Reset# pin is asserted without SLP_SUS# being asserted, then
+ * it means that there is an unexpected power loss (global reset
+ * event). In this case, check if shutdown was being forced by pressing
+ * power button. If yes, release power button.
+ */
+ if ((power_get_signals() & IN_PGOOD_ALL_CORE) && forcing_shutdown) {
+ power_button_pch_release();
+ forcing_shutdown = 0;
+ }
+}
+
+enum power_state chipset_force_g3(void)
+{
+ chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
+
+ return POWER_G3;
+}
+
+/* Called by APL power state machine when transitioning from G3 to S5 */
+void chipset_pre_init_callback(void)
+{
+ /*
+ * TODO (b/122265772): Need to use CONFIG_POWER_PP5000_CONTROL, but want
+ * to do that after some refactoring so that more than 1 signal can be
+ * tracked if necessary.
+ */
+
+ /* Enable 5.0V and 3.3V rails, and wait for Power Good */
+ /* Turn on PP5000_A rail */
+ gpio_set_level(GPIO_EN_PP5000_A, 1);
+ /* Turn on A (except PP5000_A) rails*/
+ gpio_set_level(GPIO_EN_A_RAILS, 1);
+
+ /* Ensure that PP5000_A rail is stable */
+ while (!gpio_get_level(GPIO_PP5000_A_PG_OD))
+ ;
+
+}
+
+enum power_state power_handle_state(enum power_state state)
+{
+
+ int all_sys_pwrgd_in;
+ int all_sys_pwrgd_out;
+
+ common_intel_x86_handle_rsmrst(state);
+
+ switch (state) {
+
+ case POWER_S5:
+ if (forcing_shutdown) {
+ power_button_pch_release();
+ forcing_shutdown = 0;
+ }
+ /* If RSMRST_L is asserted, we're no longer in S5. */
+ if (!power_has_signals(IN_PGOOD_ALL_CORE))
+ return POWER_S5G3;
+ break;
+
+ case POWER_S0:
+ /*
+ * Check value of PG_EC_ALL_SYS_PWRGD to see if EC_PCH_SYS_PWROK
+ * needs to be changed. If it's low->high transition, requires a
+ * 2msec delay.
+ */
+ all_sys_pwrgd_in = gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD);
+ all_sys_pwrgd_out = gpio_get_level(GPIO_EC_PCH_SYS_PWROK);
+
+ if (all_sys_pwrgd_in != all_sys_pwrgd_out) {
+ if (all_sys_pwrgd_in)
+ msleep(2);
+ gpio_set_level(GPIO_EC_PCH_SYS_PWROK, all_sys_pwrgd_in);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return common_intel_x86_power_handle_state(state);
+}
diff --git a/power/cometlake.h b/power/cometlake.h
new file mode 100644
index 0000000000..e3be31bdfb
--- /dev/null
+++ b/power/cometlake.h
@@ -0,0 +1,28 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Cometlake chipset power control module for Chrome EC */
+
+#ifndef __CROS_EC_COMETLAKE_H
+#define __CROS_EC_COMETLATE_H
+
+/* Input state flags. */
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+
+#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
+ IN_PCH_SLP_S4_DEASSERTED)
+
+#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD)
+
+#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
+ PP5000_PGOOD_POWER_SIGNAL_MASK)
+
+#define CHIPSET_G3S5_POWERUP_SIGNAL POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD)
+
+#define CHARGER_INITIALIZED_DELAY_MS 100
+#define CHARGER_INITIALIZED_TRIES 40
+
+#endif /* __CROS_EC_COMETLAKE_H */
diff --git a/power/intel_x86.c b/power/intel_x86.c
index 1cf49a6137..195671c824 100644
--- a/power/intel_x86.c
+++ b/power/intel_x86.c
@@ -29,6 +29,8 @@
#include "apollolake.h"
#elif defined(CONFIG_CHIPSET_CANNONLAKE)
#include "cannonlake.h"
+#elif defined(CONFIG_CHIPSET_COMETLAKE)
+#include "cometlake.h"
#elif defined(CONFIG_CHIPSET_ICELAKE)
#include "icelake.h"
#elif defined(CONFIG_CHIPSET_SKYLAKE)