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authorSooraj Govindan <sooraj.govindan@intel.com>2020-05-15 21:09:17 +0530
committerCommit Bot <commit-bot@chromium.org>2020-05-18 20:35:25 +0000
commitea9bcbd8a2f76cdcc341a8d183838547bf347874 (patch)
treefd6ccc8e4ed013e9008764147acd5624016369a7 /power
parent2701bf1ba764b9d0da83e837c1ac8d4608a64d11 (diff)
downloadchrome-ec-ea9bcbd8a2f76cdcc341a8d183838547bf347874.tar.gz
power/icelake: Don't cache GPIO_PCH_DSW_PWROK
There is a potential race condition for passthrough DSW_PWROK pin as the PCH_DSW_PWROK is set to low by chipset_force_shutdown() and is not updated by dsw_pwrok_pass_thru(). To avoid this, use current values of EC_DSW_PWROK and PCH_DSW_PWROK to set the passthrough value. BUG=b:150985246 BRANCH=None TEST=`make -j buildall` Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: I0249a948ea8814cbc3462630e99a471010a056df Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2204337 Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'power')
-rw-r--r--power/icelake.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/power/icelake.c b/power/icelake.c
index a40395434c..eb783a0417 100644
--- a/power/icelake.c
+++ b/power/icelake.c
@@ -156,10 +156,9 @@ static void enable_pp5000_rail(void)
static void dsw_pwrok_pass_thru(void)
{
int dswpwrok_in = intel_x86_get_pg_ec_dsw_pwrok();
- static int dswpwrok_out = -1;
/* Pass-through DSW_PWROK to ICL. */
- if (dswpwrok_in != dswpwrok_out) {
+ if (dswpwrok_in != gpio_get_level(GPIO_PCH_DSW_PWROK)) {
if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)
&& dswpwrok_in) {
/*
@@ -179,7 +178,6 @@ static void dsw_pwrok_pass_thru(void)
*/
msleep(10);
GPIO_SET_LEVEL(GPIO_PCH_DSW_PWROK, dswpwrok_in);
- dswpwrok_out = dswpwrok_in;
}
}