diff options
| author | Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> | 2018-04-20 10:58:18 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-07 16:52:26 -0700 |
| commit | 108ea1ea3314f69469e1ea71f0f44754fb96b8df (patch) | |
| tree | 8323e66eb7bc6ee4c6badb5bd99159463af27fe4 /power | |
| parent | a8f4ad9f26a35a786e17498fa4d0a513b9412856 (diff) | |
| download | chrome-ec-108ea1ea3314f69469e1ea71f0f44754fb96b8df.tar.gz | |
Fizz: add CONFIG_BOARD_HAS_RTC_RESET
This patch resets the RTC of the SoC when the system doesn't leave
S5. If it fails 5 times, the system will go back to and stay in G3.
BUG=b:79323716
BRANCH=fizz
TEST=Boot Fizz differently:
1. AC plug-in
2. Power button press
3. reboot EC command
4. servo reset button
5. Recovery mode
Change-Id: I728c99c342fb888600599acbe25f72a478ccf948
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1020583
Reviewed-on: https://chromium-review.googlesource.com/1089035
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Diffstat (limited to 'power')
| -rw-r--r-- | power/intel_x86.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/power/intel_x86.h b/power/intel_x86.h index 70a1a66e65..bfbf89538c 100644 --- a/power/intel_x86.h +++ b/power/intel_x86.h @@ -33,4 +33,9 @@ enum power_state chipset_force_g3(void); */ enum power_state common_intel_x86_power_handle_state(enum power_state state); +/** + * Reset RTC + */ +void board_rtc_reset(void); + #endif /* __CROS_EC_INTEL_X86_H */ |