diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2016-04-08 19:42:09 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-04-29 14:38:06 -0700 |
| commit | 90145968b22e9578cc2f008fa4a6947f6168d48a (patch) | |
| tree | 0aca15645c16ca173ebad6d367b0dc7096cf6b3d /power | |
| parent | 9eafb5b9ddaea2ac7f35e3a6b849541d1ca3a7ad (diff) | |
| download | chrome-ec-90145968b22e9578cc2f008fa4a6947f6168d48a.tar.gz | |
kevin: GPIO changes for new proto build
BUG=chrome-os-partner:52171
TEST=Verify old kevin boards still boot + power sequence.
BRANCH=None
Change-Id: Iacc02beba05ef3e80ffa59aa7fc5718c12bae20c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338043
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/rk3399.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/power/rk3399.c b/power/rk3399.c index c3ed2cfc08..81fff5c3a2 100644 --- a/power/rk3399.c +++ b/power/rk3399.c @@ -41,8 +41,6 @@ static const struct power_signal_info power_control_outputs[] = { { GPIO_PP900_USB_EN, 1 }, { GPIO_PP900_PCIE_EN, 1 }, - { GPIO_PP1200_HSIC_EN, 1 }, - { GPIO_PP1800_SENSOR_EN_L, 0 }, { GPIO_PP1800_LID_EN_L, 0 }, { GPIO_PP1800_PMU_EN_L, 0 }, @@ -152,8 +150,8 @@ enum power_state power_handle_state(enum power_state state) msleep(2); gpio_set_level(GPIO_PP1800_SIXAXIS_EN_L, 0); + msleep(2); gpio_set_level(GPIO_PP3300_TRACKPAD_EN_L, 0); - gpio_set_level(GPIO_PP1200_HSIC_EN, 1); /* Call hooks now that rails are up */ hook_notify(HOOK_CHIPSET_STARTUP); @@ -163,13 +161,12 @@ enum power_state power_handle_state(enum power_state state) case POWER_S3S0: gpio_set_level(GPIO_AP_CORE_EN, 1); msleep(2); - gpio_set_level(GPIO_PP3300_USB_EN_L, 0); - msleep(2); gpio_set_level(GPIO_PP1800_S0_EN_L, 0); msleep(2); gpio_set_level(GPIO_PP3300_S0_EN_L, 0); msleep(2); - msleep(10); /* TBD */ + gpio_set_level(GPIO_PP3300_USB_EN_L, 0); + msleep(2); /* Pulse SYS_RST */ gpio_set_level(GPIO_SYS_RST_L, 0); |